SLUSF78A June   2023  – November 2024 UCC28731-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Detailed Pin Description
        1. 6.3.1.1 VDD (Device Bias Voltage Supply)
        2. 6.3.1.2 GND (Ground)
        3. 6.3.1.3 HV (High Voltage Startup)
        4. 6.3.1.4 DRV (Gate Drive)
        5. 6.3.1.5 CBC (Cable Compensation)
        6. 6.3.1.6 VS (Voltage Sense)
        7. 6.3.1.7 CS (Current Sense)
      2. 6.3.2 Primary-Side Regulation (PSR)
      3. 6.3.3 Primary-Side Constant Voltage Regulation
      4. 6.3.4 Primary-Side Constant Current Regulation
      5. 6.3.5 Valley-Switching and Valley-Skipping
      6. 6.3.6 Startup Operation
      7. 6.3.7 Fault Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 7.2.2.2 Transformer Turns Ratio, Inductance, Primary-Peak Current
        3. 7.2.2.3 Transformer Parameter Verification
        4. 7.2.2.4 Output Capacitance
        5. 7.2.2.5 VDD Capacitance, CVDD
        6. 7.2.2.6 VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 7.2.3 Application Curves
    3. 7.3 Do's and Don'ts
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1  Capacitance Terms in Farads
        2. 8.1.1.2  Duty-Cycle Terms
        3. 8.1.1.3  Frequency Terms in Hertz
        4. 8.1.1.4  Current Terms in Amperes
        5. 8.1.1.5  Current and Voltage Scaling Terms
        6. 8.1.1.6  Transformer Terms
        7. 8.1.1.7  Power Terms in Watts
        8. 8.1.1.8  Resistance Terms in Ω
        9. 8.1.1.9  Timing Terms in Seconds
        10. 8.1.1.10 DC Voltage Terms in Volts
        11. 8.1.1.11 AC Voltage Terms in Volts
        12. 8.1.1.12 Efficiency Terms
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1 Design Requirements

The following table illustrates a typical subset of high-level design requirements for a particular converter, of which many of the parameter values are used in the various design equations in this section.

Table 7-1 Design Example Performance Requirements
PARAMETER CONDITIONS MIN NOM MAX UNITS
VIN AC-Line Input Voltage 85 115 / 230 264 VRMS
fLINE Line Frequency 47 50 / 60 63 Hz
VOCV Output Voltage, CV Mode VIN(min) ≤ VIN ≤ VIN(max), IOUT ≤ IOCC 4.75 5.0 5.25 V
IOCC Output Current, CC Mode VIN(min) ≤ VIN ≤ VIN(max), IOUT = IOCC 2.0 2.1 2.2 A
VRIPPLE Output Voltage Ripple VIN(min) ≤ VIN ≤ VIN(max), IOUT ≤ IOCC 80 mVpp
Output Over-Voltage Limit 5.6 V
Output Over-Current Limit 2.1 A
VIN(run) Start-Up Input Voltage IOUT = IOCC 72 VRMS
VOCC Minimum Output Voltage, CC Mode IOUT = IOCC 2 V
ηAVG Average Efficiency Average of 25%, 50%, 75% 100% Load, at VIN = 115VRMS and 230VRMS 80%
η10 Light-Load Efficiency 10 % Load, at VIN = 115VRMS and 230VRMS 75%
PSTBY Stand-by Input Power Consumption VIN = 115VRMS and 230VRMS 4.5 mW

Many other necessary design parameters, such as fMAX and VBULK(min) for example, may not be listed in such a table. These values may be selected based on design experience or other considerations, and may be iterated to obtain optimal results.