SLUSG51 October   2025 BQ25692-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Power-On-Reset
      2. 6.3.2  Battery Only Power Up State
      3. 6.3.3  Device HIZ State
      4. 6.3.4  Power Up REGN LDO
      5. 6.3.5  Default VINDPM Setting
      6. 6.3.6  Default Charge Profile Setting with CELL, ICHG and VCHG Pins
      7. 6.3.7  Buck-Boost Converter Operation
        1. 6.3.7.1 Pulse Frequency Modulation (PFM)
        2. 6.3.7.2 Switching Frequency and Dithering Feature
      8. 6.3.8  Forward (Sink) Operation
        1. 6.3.8.1 Power Path Management
          1. 6.3.8.1.1 Dynamic Power Management
            1. 6.3.8.1.1.1 ILIM_HIZ Pin
            2. 6.3.8.1.1.2 Input Current Optimizer (ICO)
        2. 6.3.8.2 Battery Charging Management
          1. 6.3.8.2.1 Battery Detection
          2. 6.3.8.2.2 Autonomous Charging Cycle
          3. 6.3.8.2.3 Battery Charging Profile
          4. 6.3.8.2.4 Charging Termination
          5. 6.3.8.2.5 Charging Safety Timer
          6. 6.3.8.2.6 CV Timer
          7. 6.3.8.2.7 Thermistor Qualification
            1. 6.3.8.2.7.1 JEITA Guideline Compliance in Charge Mode
            2. 6.3.8.2.7.2 Cold/Hot Temperature Window in Reverse Mode
        3. 6.3.8.3 Bypass Mode
      9. 6.3.9  Reverse (Source) Mode (USB On-The-Go)
        1. 6.3.9.1 Reverse (Source) Mode Operation
        2. 6.3.9.2 Backup Power Supply Mode
        3. 6.3.9.3 Reverse Bypass Mode
      10. 6.3.10 Status Outputs ( STAT, and INT)
        1. 6.3.10.1 Power Good Indicator (PG_STAT)
        2. 6.3.10.2 Charging Status Indicator (STAT Pin)
        3. 6.3.10.3 Interrupt to Host ( INT)
      11. 6.3.11 Serial Interface
        1. 6.3.11.1 Data Validity
        2. 6.3.11.2 START and STOP Conditions
        3. 6.3.11.3 Byte Format
        4. 6.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 6.3.11.5 Target Address and Data Direction Bit
        6. 6.3.11.6 Single Write and Read
        7. 6.3.11.7 Multi-Write and Multi-Read
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host Mode and Default Mode
      2. 6.4.2 Register Bit Reset
    5. 6.5 Register Map
      1. 6.5.1 BQ25692Q1 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application Design Example
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Inductor Selection
        2. 7.2.2.2 Capacitors
        3. 7.2.2.3 Buck Mode Input (VIN) Capacitor
        4. 7.2.2.4 Boost Mode Output (VOUT) Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

5.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman body model (HBM), per AEC Q100-002(1)±2000V
Charged device model (CDM), per AEC Q100-011Corner pins (BTST1, ILIM_HIZ, VCHG, BTST2)±750
All pins±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.