SLUUDG8 August   2026 MSPM0G3519 , MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Review of Software Differences Between MSPM0Gx51x and MSPM33C32xx
    1. 2.1 Development Environments
    2. 2.2 Software Porting Flow
    3. 2.3 Peripheral Differences
      1. 2.3.1 Interrupt Differences
      2. 2.3.2 ADC Differences
      3. 2.3.3 Security Differences
    4. 2.4 Communications Peripherals
      1. 2.4.1 SPI Differences
      2. 2.4.2 UART Differences
      3. 2.4.3 I2C Differences
  6. 3Summary
  7. 4References

2.4.2 UART Differences

UART Peripheral Feature UART (MSPM0SDK) UNICOMM UART (MSPM33SDK)
Wrapper Standalone UART Peripheral accessed via UART_REGS UNICOMM_Inst_regs->uart
Clock Source Enhancements
  • DL_UART_CLOCK_BUSCLK
  • DL_UART_CLOCK_MFCLK
  • DL_UART_CLOCK_LFCLK
  • DL_UART_CLOCK_BUSCLK
  • DL_UART_CLOCK_MFCLK
  • DL_UART_CLOCK_LFCLK
  • DL_UART_CLOCK_ASYNC_LFCLK
  • DL_UART_CLOCK_ASYNC_SYSCLK
  • DL_UART_CLOCK_ASYNC_HFCLK
  • DL_UART_CLOCK_ASYNC_PLL
API Compatibility macros High backwards compatability, all DL_UART_MAIN_* and DL_UART_EXTEND_* APIs are mapped to Unicomm
FIFO Management
  • DL_UART_enableFIFOs()
  • DL_UART_disableFIFOs()
 FIFO is always enabled, but APIs are still provided for backwards compatability. For example, calling DL_UART_isFIFOsENABLED() always returns true
FIFO Threshold levels
  • DL_UART_yX_FIFO_LEVEL_3_4_EMPTY
  • DL_UART_yX_FIFO_LEVEL_1_2_EMPTY
  • DL_UART_yX_FIFO_LEVEL_1_4_EMPTY
  • DL_UART_yX_FIFO_LEVEL_ONE_ENTRY
  • DL_UART_yX_FIFO_LEVEL_EMPTY
  • DL_UART_yX_FIFO_LEVEL_3_4_EMPTY
  • DL_UART_yX_FIFO_LEVEL_1_2_EMPTY
  • DL_UART_yX_FIFO_LEVEL_1_4_EMPTY
  • DL_UART_yX_FIFO_LEVEL_ONE_ENTRY
  • DL_UART_yX_FIFO_LEVEL_EMPTY
  • DL_UART_yX_FIFO_LEVEL_ALMOST_EMPTY
  • DL_UART_yX_FIFO_LEVEL_ALMOST_FULL
Preemption Additions No compatible features on the MSPM0Gx51x
  • DL_UART_IIDX_PREEMPT_INT_TX
  • DL_UART_IIDX_PREEMPT_INT_RX
  • DL_UART_INTERRUPT_LINE_TIMEOUT
  • DL_UART_IIDX_LINE_TIMEOUT
Register naming
  • Control: CTLx
  • Line Control: LCRH
  • Status: STAT
  • TX Data: TXDATA
  • RX Data: RXDATA
  • Baud Rate: IBRD/FBRD
  • Control: CTLx
  • Line Control: LCRH
  • Status: STAT
  • TX Data: TXDATA
  • RX Data: RXDATA
  • Baud Rate: IBRD/FBRD
Power Management
  • DL_UART_enablePower(UARTx)
  • DL_UART_enablePower(UNICOMM0)
  • DL_UNICOMM_enablePower(unicomm)
Backup/Restore Configuration
  • DL_UART_Main_backupConfig
  • DL_UART_Extend_backupConfig
  • DL_UART_Main_saveConfiguration()
  • DL_UART_Extend_saveConfiguration()
  • DL_UART_backupConfig
  • DL_UART_saveConfiguration()
  • DL_UART_restoreConfiguration()
Analog Glitch Filter No analog filter in MSPM33C.
Unmentioned Core Functionalities UART_Regs_* used UNICOMM_Inst_Regs_* used
API Compatibility macros High backwards compatability, all DL_UART_MAIN_* and DL_UART_EXTEND_* APIs are mapped to Unicomm