SLVAEG1A August   2019  – May 2021 TLV62568 , TLV62568A , TPS62840

 

  1.   Trademarks
  2. 1Introduction
  3. 2Highlighted Products
  4. 3Buck Converter Architectures
  5. 4Testing Setup
  6. 5Testing Results
  7. 6Results Summary
  8. 7Further Reading
  9. 8Revision History

Testing Results

PARAMETER ARCHITECTURE A ARCHITECTURE B ARCHITECTURE C
IQ (Load = 0 A, Device Enabled) 34 µA 2.7 mA 75 nA
Light Load (ILOAD = 10 µA)
System Efficiency 10% 0.1% 93%
Stage 1 Ripple 22.4 mV 6.0 mV 5.20 mV
1.87% Accuracy 0.50% Accuracy 0.43% Accuracy
GUID-A3255213-5F56-4FC8-998C-DCE8BC600207-low.pngArchitecture A at 10 µA load. Both pre- and post-LDO ripples shown in dark blue and light blue, respectively. LDO rejects > 50 dB at 20 Hz PFM frequency GUID-13B90E79-99FD-4CB2-8722-91F609EB1846-low.pngArchitecture B at 10 µA load. Ripple (dark blue) and FFT plot of ripple (red) showing expected PWM ripple at 1.5 MHz GUID-F92D8E66-CA82-4E69-8869-A98DA482B7C5-low.pngArchitecture C at 10 µA load. Both pre-and post-PI filter ripples shown in dark blue and light blue, respectively. PI filter rejects only 3 dB at 100 Hz PFM frequency
Stage 2 Ripple Noise Floor N/A 3.60mV
<0.01% Accuracy 0.30% Accuracy
Full Load (ILOAD = 200 mA)
System Efficiency 61% 91% 88%
Stage 1 Ripple 28.0 mV 6.0 mV 3.68 mV
2.33% Accuracy 0.50% Accuracy 0.31% Accuracy
GUID-B71E5BDE-CED6-4272-8A16-165F760D7635-low.pngFFT plot for ripple before LDO with 6.5 MHz bandwidth; cursors at low frequency 200 kHz peak and nominal switching frequency 1.5 MHz peak GUID-97648144-2D42-4090-8142-F204B37A3CC8-low.pngFFT plot shown for FPWM ripple with 6.25 MHz bandwidth; cursors at nominal switching frequency 1.5 MHz and first harmonic 3 MHz peaks GUID-0DB5D155-3C8A-44F8-B13C-2DCF2F4FFC84-low.pngFFT plot for ripple before PI filter with 6.25 MHz bandwidth; cursors at nominal switching frequency 1.8 MHz and first harmonic 3.6 MHz peaks
Stage 2 Ripple 7.6 mV N/A Noise Floor
0.63% Accuracy <0.01% Accuracy
GUID-117036CF-13E1-43B9-A9FE-5E57328914CD-low.pngFFT plot for ripple after LDO with 6.5 MHz bandwidth; cursors in same spots showing expected 22 dB rejection by TPS7A05 at 1.5 MHz GUID-C61E276C-5FD1-4F9F-90B8-CA6C46385578-low.pngFFT plot for ripple after PI filter with 6.25 MHz bandwidth; cursors in same spots showing ripple after PI filter reaches noise floor of oscilloscope (85–90 dB)
Thermal Images Taken after 20 minutes on with 200 mA load current GUID-A1B81288-A4E8-443C-8C9F-B1F6312B9452-low.png
Infrared image showing TLV62568 heating to 28.8°C and TPS7A05 heating to 50.6°C after 20 minutes
GUID-9764EC51-8014-440A-B4D9-66654D5AF4A5-low.pngInfrared image showing TLV62568A heating to 22.5°C after 20 minutes GUID-C6F5B526-C592-4742-9AF8-B54621054C57-low.png
Infrared image showing TPS62841 heating to 23.3°C after 20 minutes
Transient - Switching Load (Square wave, 50uA-200mA, 1kHz)
Stage 1 Ripple GUID-CD9674D5-1BAE-4321-89DA-23992609C4B8-low.pngDynamically changing operation mode (PFM-PWM-PFM) with load change. FFT plot before LDO with 4 MHz bandwidth, showing several frequency spikes as PFM frequency changes to PWM GUID-69DB13F0-1679-4C5D-A2A5-1B79AEB2DE1E-low.pngOutput ripple continues to be PWM as load changes, with minimal overshoot and undershoot at load step. FFT plot with 2.5 MHz bandwidth shows ripple at 1.5 MHz, as expected GUID-DDE2E31C-D680-48B2-935E-DFD90B07ED98-low.pngDynamically changing operation mode (PFM-PWM) with load change. FFT plot before PI filter with 4.25 MHz bandwidth, showing ripple primarily at very low frequencies (PFM) and switching frequency (1.8 MHz)
Stage 2 Ripple GUID-C323F724-9AF5-462D-9B07-75CF81807CA2-low.pngFFT plot after LDO with 4 MHz bandwidth shows higher overshoot and undershoot values (low frequency) and strong noise attenuation by LDO N/A GUID-D97240CF-8E7F-4882-8CB1-9F0D2FA4CC46-low.pngFFT plot after PI filter with 4.25 MHz bandwidth, showing undershoot and overshoot present, though smaller than values in Architecture A, and very strong noise attenuation by PI filter
Overshoot (at output of architecture) 24 mV 3 mV 6 mV
Overshoot Settling Time 125 µs 60 µs 166 µs
Undershoot (at output of architecture) 76 mV 3 mV 8 mV
Undershoot Settling Time 129 µs 29 µs 96 µs