SLVAEJ5C February   2020  – December 2020 TPS62810-Q1 , TPS62811-Q1 , TPS62812-Q1 , TPS62813-Q1

 

  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)
  5. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS6281x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS6281x-Q1 datasheet.

GUID-26AB7A82-0C90-452E-A008-4F4E2F97DE3E-low.gifFigure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Assumption the device is running in the typical application, please refer to the 'Simplified Schematics' on the 1st page in the TPS62810-Q1 datasheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to GND
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Intended functionality.D
VIN2Device does not power up.B
SW3Potential device damage.A
GND4No effect.D
FB5Output voltage regulated to VIN (100% mode).B
SS/TR6Device not functional.B
COMP/FSET7Intended functionality.D
EN8Intended functionality.D
PG9Intended functionality.D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Undetermined device operation.B
VIN2Device does not power up.B
SW3Device not functional, open loop operation.B
GND4Device not functional.B
FB5Undetermined output voltage behavior; open loop operation.B
SS/TR6Intended functionality.D
COMP/FSET7Intended functionality.D
EN8Undetermined device operation; device might power up or not.B
PG9Intended functionality.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1PGDevice runs FPWM mode once PG is high impedance.B
FB5SS/TRUndetermined device operation, VOUT spikes up to VINB
SS/TR6COMP/FSETUndetermined device operation.B
EN8PGDevice does not power up.B
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Intended functionality: Forced PWM.D
VIN2Intended functionality.D
SW3Potential device damage.A
GND4Device does not power up.B
FB5Potential device damage.A
SS/TR6Intended functionality.D
COMP/FSET7Intended functionality.D
EN8Intended functionality.D
PG9Potential device damage.

A