SLVAF30 February 2021 TPS55288 , TPS61021A , TPS61022 , TPS61023 , TPS61088 , TPS61089 , TPS61178 , TPS61230A , TPS61235P , TPS61288 , TPS61378-Q1

The voltage spike shown in Figure 2-3 is caused by the ESR (effective series resistance) and ESL (effective series inductance) of the output capacitor. The Figure 3-1 shows the impedance of a 0805-package ceramic capacitor over frequency. Point A is the resonant frequency of the ESL and the capacitor.

The impedance of the capacitor is equal to its ESR which is approximately 3.5mΩ. The impedance of the capacitor increases linearly once the frequency is higher than 10 MHz. This is behavior of the ESL. From the impedance of point B and point C, the ESL is estimated to be 0.27nH.

The voltage crossing the ESR is in proportion to the current through capacitor. A ceramic capacitor has only several milliohm resistances and normally there will be several ceramic capacitors in parallel. Thus, this voltage ripple caused by ESR is small and can be neglected.

The voltage crossing the ESL is in proportional to its di/dt, which could be very large. Because the switching frequency of a boost converter always tends to be as large as possible to reduce the solution size. The di/dt will also increase with the switching frequency to reduce the power loss in the IC.

Considering the ESL and the parasitic
inductance of the PCB trace and IC package, the schematic of the boost converter power
stage is shown in Figure 3-2 where L_{PAR1} is the sum of pin-out and PCB parasitic inductor and
L_{PAR2} is the parasitic inductor of the GND pin;

When Q_{1} turns off and SW node
voltage is higher than V_{OUT}, the inductor current starts to transit from
Q_{1} to Q_{2}. During the current transition period, the equivalent
circuit is shown in Figure 3-3, where

- C
_{Q1}represents parasitic capacitor of Q_{1}. The turning-off time of Q_{1}is neglected. - I
_{L1}represents the inductor as inductor current is almost constant during the short transition period. - V
_{COUT}represent the voltage in the ideal capacitance portion of the output capacitor. the voltage is almost constant during this transition period.

The Figure 3-3 can be further simplified to a LC circuit with initial inductor current
I_{L1}. The inductor value is the sum of all the parasitics inductor in the
circuit. The capacitor is C_{Q1}. So the voltage spike of the ESL is defined by
Equation 2. The voltage spike is in proportinal to inductor current.

Equation 2.

And the oscillation frequency is defined by Equation 3.

Equation 3.

When Q_{1} turns on, the inductor
current firstly transits from Q_{2} to Q_{1}, then voltage
Q_{1} quickly declines to zero. The simplified schematic during this period
is shown in Figure 10, where C_{Q2} represents the parasitic capacitance of
Q_{2} when it turns off.

The maximum voltage spike at ESL is
defined by Equation 4. The circuit can also be simplified to a LC circuit. The V_{ESL} voltage
level is in proportion to the boost output voltage, and the oscillation frequency is the
same as Equation 3 because the C_{Q2} and C_{Q1} is similar.

Equation 4.

Taking TPS61022EVM as example,
C_{Q1} and C_{Q2} are approximately 0.4 nF. L_{PAR1} is
closed to 0.3 nH; L_{PAR2} is approximately 0.05 nH; ESL is approximately 0.09
nF as there are three capacitors in parallel. Thus, the LC oscillation frequency is up
to 300 MHz.

At VIN=3.6V,
VOUT=5V, IOUT=3A condition, the I_{L1} is about 4.4 A. The V_{ESL} spike
at both Q_{1} turning on and turning off condition are approximately 0.75 V.
however, the actual voltage spike from Figure 2-3 is lower than this calculation result, especially at Q_{1} turning-on
condition. The main factor leading to the gap is the turning on/off time of the
Q_{1}. The turning on/off time of Q_{1} is at 5ns level. The greatly
impacts the voltage spike caused by a 300-MHz LC ringing. It is hard to have an equation
to calculate the voltage spike if considering the turning on/off time. A better method
is simulation with PSPICE-FOR-TI or other tools.