SLVAFE6 December   2022 TPS62870 , TPS62870-Q1 , TPS62871 , TPS62871-Q1 , TPS62872 , TPS62872-Q1 , TPS62873 , TPS62873-Q1 , TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1 , TPS6287B10 , TPS6287B25 , TPSM8287A06 , TPSM8287A12 , TPSM8287A15

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Configuration
  5. 3Measurements
    1. 3.1 DC Regulation in PWM and Power Save Mode Operation
    2. 3.2 Transient Performance
    3. 3.3 Control Loop Gain
  6. 4Summary
  7. 5References

2 Configuration

Figure 2-1 shows how this resistor divider must be connected. In the layout of the TPS62873EVM-143 and TPS62873EVM-144 footprints for those resistors are already provided.

Figure 2-1 Resistor Divider

The output voltage then is defined by the fixed output voltage selected using VSEL and of course the values of the resistors used in this divider. Equation 1 shows how to calculate the output voltage.

Equation 1. V O U T = V O U T f i x e d ∙ R 12 + R 11 R 11

As Equation 1 shows, the fixed output voltage VOUTfixed must be selected lower than the desired final output voltage.

The first obvious tradeoff of this approach is the loss of accuracy due to the tolerance of the resistor values and their temperature drift. This can be kept at a minimum by selecting a fixed output voltage version with an output voltage as close as possible to the desired final output voltage. The additional error for the minimum and the maximum output voltage of this configuration can be calculated using Equation 2 and Equation 3. An additional error is generated by the bias current flowing into the VOSNS pin. This bias current must flow through R12 which causes an increase of the output voltage. The resulting error can be kept negligible by using a low resistance value for R12. A resistor value in the range of 1 kΩ makes this error negligible for the TPS6287x devices.

Equation 2. V O U T m i n = V O U T f i x e d ∙ ( 1 - ∆ V O U T ) ∙ R 12 ∙ 1 - ∆ R 12 + R 11 ∙ ( 1 + ∆ R 11 ) R 11 ∙ ( 1 + ∆ R 11 )
Equation 3. V O U T m a x = V O U T f i x e d ∙ ( 1 + ∆ V O U T ) ∙ R 12 ∙ 1 + ∆ R 12 + R 11 ∙ ( 1 - ∆ R 11 ) R 11 ∙ ( 1 - ∆ R 11 )

Another important consideration is maintaining AC control performance. The resistors of the resistive divider, especially the upper resistor R12 in the VOSNS path, creates low pass filters together with parasitic capacitances at the VOSNS and GOSNS pins. To mitigate this effect a feed-forward capacitor Cff in parallel to R12 can be added. Equation 4 shows how to estimate an appropriate value for this capacitor. fCO in this equation is the expected crossover frequency of the control loop.

Equation 4. C f f = 2 π ∙ f C O ∙ R 12

In case of the TPS6287x devices a total resistance in the range of 10 kΩ for the resistor divider and limiting the increase of the output voltage to a maximum of 20% is a good choice for getting negligible impact on the control performance.

If for example an output voltage of 1.2 V is needed, the TPS6287x-Q1 devices can be configured to a fixed output voltage of 1 V as described in the TPS6287x-Q1 2.7-V to 6-V Input, 6-A, 9-A, 12-A, 15-A, Automotive, Stackable, Synchronous Step-Down Converters with Fast Transient Response data sheet. With the recommendations and equations described above, an output voltage of 1.2 V can be configured with a resistive divider using 2 kΩ for R12 and 10 kΩ for R11. Assuming the resistor accuracy of both resistors is 1%, the accuracy of the output voltage changes from the initial +/- 1% specified for the 1 V fixed output voltage to +/- 1.3% which can be acceptable in most of the cases. Assuming a crossover frequency of 300 kHz, 1 nF is an appropriate value calculated for Cff for this configuration.

With the feedback divider, the voltages which can be set with the interface change as well. The default values defined in the registers scale with the gain of the feedback divider. Equation 5 shows how to calculate the new regulated output voltage for a dedicated voltage setting VOUT_Reg in the VSET registers.

Equation 5. V O U T = V O U T _ R e g ∙ R 12 + R 11 R 11

If the feedback divider for example is designed to increase the output voltage by 20%, a programmed output voltage of 0.4 V in the VSET registers results in a regulated output voltage of 0.48 V.