SLVAFV8A July   2024  – July 2025 TPS25751

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2ADCINX Setting
  6. 3Unique Address Interface Protocol
  7. 4PTCH Mode to APP Mode
    1. 4.1 Step of PTCH Mode to APP Mode
    2. 4.2 Step of Generating Low Region Binary
  8. 5Example Code
  9. 6References
  10. 7Revision History

4.1 Step of PTCH Mode to APP Mode

  1. I2Ct_IRQ == Low:

    Upon a cold boot (power cycle or GAID), the PD controller enters PTCH mode and only the Ready for Patch[81] interrupt is enabled automatically. The interrupt registers can be updated while in PTCH mode. This PBM implementation uses the Ready for Patch and CMD1 complete interrupts. The primary reason for using interrupts instead of polling the registers is to reduce the PD controller CPU loading to just the activities associated with the commands.

    The Ready for Patch interrupt is used at the beginning of the PBM process to indicate that the PD controller is ready. The CMD1 complete interrupt is used to alert the EC that the PBMs and PBMc commands are complete. Polling of the MODE register, 0x03, is still included in this example to account for the time when the patch is loaded but the PD controller is not yet transitioned to the application mode: APP.

  2. Mode == PTCH:

    PTCH and APP modes are described in the PD controller TRMs. The EEPROM on the PD controller EVM is disabled (SDA disconnected) and therefore the PD controller transitions to and stays in PTCH mode. The check for the PTCH mode at the beginning of the process is not necessary but included for completeness. The following is the example for the command and the logic analyzer capture is shown in Read PTCH Mode.

    [0x21] + ACK (Unique Address/Wr/A)

    0x03 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x04 (Byte Count)

    0x50 0x54 0x43 0x48 (PTCH in 4ASCII characters)

    Read PTCH Mode Figure 4-2 Read PTCH Mode
  3. Configure I2Ct_IRQ, CMD1 Complete:

    The CMD1 complete interrupt is used to alert the EC that the PBMs command is complete. Setting the Interrupt Mask and clearing the interrupts are accomplished with registers 0x16 and 0x18, respectively. See 1 and 2

    [0x21] + ACK (Unique Address/Wr/A)

    0x16 + ACK (Register Number/A)

    0x0B (Byte Count)

    0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x01 (MSB)

    Configuring the Interrupt Mask Register, 0x16 Figure 4-3 Configuring the Interrupt Mask Register, 0x16

    [0x21] + ACK (Unique Address/Wr/A)

    0x18 + ACK (Register Number/A)

    0x0B (Byte Count)

    0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF (MSB)

    Interrupt Clear Register, 0x18 Figure 4-4 Interrupt Clear Register, 0x18
  4. PBMs Data Only:

    The PBMs command is defined in the TRM reference. For this example, the parameters for PBMs are listed in Table 4-1.

    Table 4-1 PBMs Configuration: DATA1 Register
    Description Value Comment
    Bundle Size 0x00002C80 See Section 5
    I2C Burst Data Target Address 0x30 0x30, See reference 1.
    Timeout 0x31 3.1 seconds; see reference 1

    [0x21] + ACK (Unique Address/Wr/A)

    0x09 + ACK (Register Number/A)

    0x06 (Byte Count)

    0x80 0x2C 0x00 0x00 0x30 0x32 (bundle size, I2C target address, timeout value)

    DATA1 Register, 0x09, for PBMs Figure 4-5 DATA1 Register, 0x09, for PBMs
  5. Data Good:

    Sending the PBMs command requires writing to the DATA register multiple times. In the example, the values of 0x09 are confirmed before writing the PBMs command in register 0x08. There is a delay of 500us between the writing to and reading from register 0x09.

    [0x21] + ACK (Unique Address/Wr/A)

    0x09 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x40 (Byte Count)

    0x00 0x00 0x00 0x00 0x00 0x00 (incorrect, rewrite DATA1)

    0x80 0x2C 0x00 0x00 0x30 0x32 (correct, proceed to writing CMD1)

  6. PBMs CMD1:

    After confirming DATA1, then write CMD1 = PBMs. The I2Ct_IRQ asserts low as shown in Figure 4-6.

    [0x20] + ACK (Unique Address/Wr/A)

    0x08 + ACK (Register Number/A)

    0x04 (Byte Count)

    0x50 0x42 0x4D 0x73 (PBMs in 4ASCII characters)

    Write PBMs to CMD1 Register, 0x08 Figure 4-6 Write PBMs to CMD1 Register, 0x08
  7. I2Ct_IRQ == Low

    The IRQ signal represents when the CMD1 Complete event has occurred and the CMD1 and DATA registers can be read to confirm the outcome of the PBMs command. The expected results are shown in steps 8 and 9.

  8. CMD1 Clear (PBMs)

    The command register, 0x08, indicates that the command is successfully completed when the content of the register is cleared. For simplicity the example only checks the first bit to confirm that the contents are not “!CMD” which indicates that the PBMs command was corrupted or the DATA register was loaded with an illegal value(1).

    [0x21] + ACK (Unique Address/Wr/A)

    0x08 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x04 (Byte Count)

    0x00 0x00 0x00 0x00

  9. DATA1 Clear (PBMs)

    The data register, 0x09, indicates a successful patch when the first byte, PatchStartStatus, is cleared. Non-zero values of PatchStartStatue, 0x04, 0x05, and 0x06, indicate invalid bundle size, target address, or timeout value, respectively. See 1.

    [0x21] + ACK (Unique Address/Wr/A)

    0x09 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x40 (Byte Count)

    0x00 0x00 0x00 0x00 0x30 0x31

  10. Burst Data

    In this step the PMBUS format is not used and the contents of the binary image are written directly to the I2C Burst Data Target Address, specified in the PBMs command, table reference. The burst format is impacted by the MCU architecture. In this case, the burst size is limited to 4KB so three successive bursts (4095bytes, 4095bytes, and 3202bytes) are sent to the PD with a 500us delay between each burst. An additional 500us delay is added to delay when the PBMc command is sent relative to the end of the final burst.

    [0x30] + ACK (Unique Address/Wr/A)

    lowRegion_i2c_array[0], lowRegion_i2c_array[1]..., lowRegion_i2c_array[4094]

    [0x30] + ACK (Unique Address/Wr/A)

    lowRegion_i2c_array[4095], lowRegion_i2c_array[4096]..., lowRegion_i2c_array[8189]

    [0x30] + ACK (Unique Address/Wr/A)

    lowRegion_i2c_array[8190], lowRegion_i2c_array[8191]..., lowRegion_i2c_array[11391]

  11. Configure I2Ct_IRQ, CMD1 Complete

    The CMD1 complete interrupt is used to alert the EC that the PBMc command is complete. Setting the Interrupt Mask and clearing the interrupts are accomplished with registers 0x16 and 0x18, respectively. The interrupt mask was already set in step 3. Repeat clearing the interrupt as shown in Figure 4-4 and Figure 4-7.

  12. PBMc CMD1 Only

    The PBMc command does not include input data so the command only is sent.

    [0x21] + ACK (Unique Address/Wr/A)

    0x08 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x04 (Byte Count)

    0x50 0x42 0x4D 0x63 (‘PBMc’ in 4ASCII characters)

    Clear Interrupts and Write PBMc to CMD1 Register Figure 4-7 Clear Interrupts and Write PBMc to CMD1 Register
  13. I2Ct_IRQ == Low

    The IRQ signal represents when the CMD1 Complete event has occurred and the CMD1 register can be read to confirm the outcome of the PBMc command.

  14. CMD1 Clear (PBMc)

    Similar to the PBMs CMD1 clear the CMD1 register is read and confirmed to be cleared of the original command and not equal to !CMD.

    Read CMD1 After I2Ct_IRQ Asserted (PBMc) Figure 4-8 Read CMD1 After I2Ct_IRQ Asserted (PBMc)
  15. Delay 20ms(1)

    The 20ms delay allows the PD controller to load and apply the image. Once the delay elapses, the DATA1 and Mode registers are read to confirm the success.

    Delay Between CMD1 and DATA1 register reads Figure 4-9 Delay Between CMD1 and DATA1 register reads
  16. DATA1 Clear (PBMc)

    In this instance, 40 bytes are read from the DATA1 register.

    Read DATA1 Register after PBMc complete Figure 4-10 Read DATA1 Register after PBMc complete
  17. Mode == APP

    The final step is to verify that the PD has transitioned to the APP mode. Once in APP mode, the PD controller is now operational with the custom configuration applied.

    [0x21] + ACK (Unique Address/Wr/A)

    0x03 + ACK (Register Number/A)

    [0x21] + ACK (Unique Address/R/A)

    0x04 (Byte Count)

    0x41 0x50 0x50 0x20 ('APP ' in 4 ASCII characters)

    APP Mode Figure 4-11 APP Mode
1. If the IRQ for CMD1 complete was not used then the CMD1 register can be polled until the contents transition from [0x50, 0x42, 0x4D, 0x73] to either [0x00, 0x00, 0x00, 0x00] or [0x21, 0x43, 0x4D, 0x44]. CMD1[0]=0x21 indicates that the command completed unsuccessfully and CMD1[0]=0x00 indicates successful completion.
1. The 20ms delay can be replaced with the Patch Loaded interrupt. No reduction in time was achieved using this interrupt in place of the delay. Therefore the 20ms delay described in the device TRMs is maintained in this document. See 1 and 2