SLVAFV8A July   2024  – July 2025 TPS25751

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2ADCINX Setting
  6. 3Unique Address Interface Protocol
  7. 4PTCH Mode to APP Mode
    1. 4.1 Step of PTCH Mode to APP Mode
    2. 4.2 Step of Generating Low Region Binary
  8. 5Example Code
  9. 6References
  10. 7Revision History

3 Unique Address Interface Protocol

The patch burst mode (PBM) feature uses both the SMBUS protocol and a simple I2C write. The SMBUS protocol is described in the data sheet (see 3and 4) and applicable to all register accesses. Register write and read examples used in PBM are listed in SMBUS Register Write Example and SMBUS Register Read Example. After the PBMs command is issued using the SMBUS protocol, the I2C writes are to the target address established in the PBMs command. I2C Patch Burst Mode Write shows the simple I2C writes for sending the image to the PD controller.

Table 3-1 SMBUS Register Write Example
TYPE ACK ADDRESS READ DATA DESCRIPTION
start
address TRUE 0x21 FALSE PD I2C Address for register access
data TRUE 0x08 Register Address
data TRUE 0x04 Number of bytes (sent to target)
data TRUE 0x50 P
data TRUE 0x42 B
data TRUE 0x4D M
data TRUE 0x73 S
stop
Table 3-2 SMBUS Register Read Example
TYPE ACK ADDRESS READ DATA DESCRIPTION
start
address TRUE 0x21 FALSE PD I2C Address for register access
data TRUE 0x09 Register Number
start Repeated Start to change from Write to Read
address TRUE 0x21 TRUE PD I2C Address for register access
data TRUE 0x40 Number of Bytes(1)
data TRUE 0x00
data TRUE 0x00
data TRUE 0x00
data TRUE 0x00
TRUE 0x30 PBM Address
FALSE 0x31 Timeout. Controller NACKs the last byte to be read.
stop
Table 3-3 I2C Patch Burst Mode Write
TYPE ACK ADDRESS READ DATA DESCRIPTION
start
address TRUE 0x30 FALSE PBM I2C Address
data TRUE 0x01 Image Byte 0
data TRUE 0x00 Image Byte 1
data TRUE 0xE0 Image Byte 2
data TRUE 0xAC Image Byte 3
Bytes 4 through 4093
data TRUE Image Byte 4094
stop(1)
start
address TRUE 0x30 FALSE PBM I2C Address
data Image Byte 4095
Bytes 4096 through 11390
data TRUE 0x00 Image Byte 11391
stop
1. The controller can choose to read all of the bytes or only a selection of bytes. In this example the controller only received 6 bytes, nacking, the last byte. In the final read of the DATA1 regsiter, 0x09, all 0x40 bytes are read.
1. The EC is limited to a transmit size of 4095 bytes. The PD controller auto-increments the PBM address pointer and is not reset by the I2C start or stop. The PBM pointer can be reset by issuing a PBMs command.