SLVAG28 May   2025 LP8764-Q1 , TPS6594-Q1

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2Overview of Main Modules
    1. 2.1 NVM and Registers
      1. 2.1.1 Register Paging
      2. 2.1.2 NVM and Register Map
    2. 2.2 Finite State Machine (FSM)
      1. 2.2.1 FFSM
      2. 2.2.2 Interrupt Handling Mechanism
      3. 2.2.3 PFSM
    3. 2.3 SPMI Communication Mechanism
  5. 3References

1 Introduction

The TPS6594 and LP8764 families are TI's next-generation PMICs, offering high integration, scalability, and functional safety. The TPS6594 integrates five BUCK converters and four LDOs internally, along with a rich set of GPIOs that can be configured via the NVM to achieve a variety of functions, including external wake-up input, watchdog feed input, enable input, external voltage monitoring input, and enable control for external high-side switches/LDOs/BUCKs, further enhancing the scalability of the device. The LP8764 chip shares a similar architecture with the TPS6594 and is often used in systems as a secondary PMIC for the TPS6594. The TPS6594 and LP8764 use SPMI interfaces for state synchronization among multiple PMICs, and the state machines of multiple PMICs operating in parallel can be considered as a whole. In terms of functional safety, they are developed to satisfy ISO26262 requirements during the design phase and incorporate a number of functional safety detection mechanisms to support ASIL D functional safety.