SLVAG33 August 2026 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
The root cause of the problem lies in the control hierarchy relationship between the two register bits HBx_OLD_DIS and HBx_LOLD_EN:
HBx_OLD_DIS = 1b completely disables all OLD detection functions for that half-bridge, including Active OLD, Negative-Current OLD, and Low-Current LOLD. This bit is the master switch for OLD and has the highest priority.
The scenario for HBx_LOLD_EN = 1b is: under the premise that OLD is globally enabled (HBx_OLD_DIS = 0b), the OLD threshold of the low-side FET of that half-bridge is switched to the low-current mode (IOLD_LOW), while simultaneously disabling OLD detection for the high-side FET to prevent the high-side FET from generating false alarms due to the excessively low IOLD_LOW threshold.
Therefore, when HBx_OLD_DIS = 1b, regardless of the value of HBx_LOLD_EN, the entire OLD function is turned off and LOLD cannot operate.
The complete OLD/LOLD control logic is shown in the table below:
| HBx_OLD_DIS | HBx_LOLD_EN | LS FET OLD | HS FET OLD | OLD Threshold | Fault Reporting |
|---|---|---|---|---|---|
| 0b | 0b | Enabled | Enabled | IOLD (Active OLD) | Enabled |
| 0b | 1b | Enabled | Disabled | IOLD_LOW(LOLD) | Enabled |
| 1b | / | Disabled | Disabled | / | Disabled[DW1] |