SLVS816B July   2008  – January 2025 TPD8S009

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 IEC 61000-4-2 ESD Protection
      2. 6.3.2 IEC 61000-4-5 Surge Protection
      3. 6.3.3 I/O Capacitance
      4. 6.3.4 Low Leakage Current
      5. 6.3.5 Supports High-Speed Differential Data Rates
      6. 6.3.6 Ioff Feature
      7. 6.3.7 Industrial Temperature Range
      8. 6.3.8 Easy Straight Through Routing
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Signal Range on High Speed TMDS Pins
        2. 7.2.2.2 Bandwidth on High-Speed TMDS Pins
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.2 IEC 61000-4-5 Surge Protection

The I/O pins can withstand surge events up to 2.5A and 25W (8/20µs waveform). An ESD and surge clamp diverts this current to ground.