SLVSAI3D September   2010  – May 2025 TPS736-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Transient Response
      3. 6.3.3 Reverse Current
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable Pin and Shutdown
      2. 6.4.2 Dropout Voltage
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application Circuit for Fixed-Voltage Versions
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input And Output Capacitor Requirements
          2. 7.2.1.2.2 Output Noise
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Application Circuit for Adjustable-Voltage Version
        1. 7.2.2.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
      2. 7.4.2 Layout Examples
  9. 8 Device And Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, And Orderable Information

6.4.1 Enable Pin and Shutdown

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5V (maximum) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate. A VEN above 1.7V (minimum) turns the regulator on and the output ramps back up to a regulated VOUT (see Figure 5-39).

When shutdown capability is not required, EN can be connected to VIN. However, the pass gate cannot be discharged using this configuration, and the pass transistor can be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output can overshoot upon power-up.

Current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section for more information.