SLVSE46A November 2017 – January 2018 TPS65680
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Time between successive GSP channels | 511 | SEQ_CLK cycles | ||||
| Time between successive GCK channels | 255 | SEQ_CLK cycles | ||||
| Time between LS_START rising edge and GSP1 toggling | 5 | SEQ_CLK cycles | ||||
| Time between LS_START rising edge and GCK1 toggling | 7 | SEQ_CLK cycles | ||||
Figure 1. LN_CLK Timing Requirements
Figure 2. LS_START Timing Requirements
Figure 3. I2C Data Transmission Timing