SLVSEI3D October   2018  – May 2026 TPS25982

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Protection (UVLO and UVP)
      2. 7.3.2 Overvoltage Protection (OVP)
      3. 7.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 7.3.3.2 Circuit Breaker
        3. 7.3.3.3 Active Current Limiting
        4. 7.3.3.4 Short-Circuit Protection
      4. 7.3.4 Overtemperature Protection (OTP)
      5. 7.3.5 Analog Load Current Monitor (IMON)
      6. 7.3.6 Power Good (PG)
      7. 7.3.7 Load Detect/Handshake (LDSTRT)
    4. 7.4 Fault Response
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
        2. 8.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 8.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 8.2.2.4 Selecting the Current Monitoring Resistor: RIMON
        5. 8.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 8.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 8.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 8.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 8.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 8.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Optical Module Power Rail Path Protection
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Device Selection
        3. 8.3.1.3 External Component Settings
        4. 8.3.1.4 Voltage Drop
        5. 8.3.1.5 Application Curves
      2. 8.3.2 Input Protection for 12V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Transient Protection
      2. 8.4.2 Output Short-Circuit Measurements
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.6 Setting the Load Handshake (LDSTRT) Delay

To indicate a successful start-up, the load circuit must provide a handshake signal to TPS25982 by pulling down the LDSTRT pin within the time set by the capacitor CLDSTRT on the LDSTRT pin. Once the PG asserts, the device sources 2μA current into CLDSTRT. For a successful handshake, the load circuit must pull-down the LDSTRT pin before CLDSTRT charges up to 1.2V.

For the design requirement of 60ms handshake delay, use Equation 29 to calculate CLDSTRT

Equation 29. C L D S T R T = I L D S T R T × t L D S T R T V L D S T R T = 2 μ A × 60 m s 1.2 V = 0.1 μ A

Select the closest available standard value: 0.1µF, 10%.