SLVSFO5E April   2020  – February 2026 TLV841

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Transient Immunity
      2. 7.3.2 SENSE Input (TLV841S)
        1. 7.3.2.1 SENSE Hysteresis
        2. 7.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 7.3.3 User-Programmable Reset Time Delay for TLV841C Only
      4. 7.3.4 Manual Reset (MR) Input for TLV841M only
      5. 7.3.5 Output Logic
        1. 7.3.5.1 RESET Output, Active-Low
        2. 7.3.5.2 RESET Output, Active-High
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VPOR)
      2. 7.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Adjustable Voltage Supervisor With Push-Button Functionality
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves: TLV841EVM
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.3 Detailed Design Procedure

The TLV841SADL01 can monitor any voltage above 0.505V using an external voltage divider. This device has a negative going input threshold voltage of 0.505V; however, the design needs to assert a reset when VDD drops below 2.90V. By using a resistor divider (R1 = 47.5 kΩ, R2 = 10kΩ) the negative going threshold voltage becomes 2.90V. The device's positive going voltage threshold is VIT- + VHYS. The typical VHYS is 25mV. This in combination with the resistor divider makes the design's positive going threshold voltage equal to 3.05V. If VDD falls below 2.90V, RESET will assert. If VDD rises above 3.05V, RESET will deassert. See Figure 8-2 for a timing diagram detailing the voltage levels and reset assertion/deassertion conditions.

TLV841 Design 1 Timing Diagram Figure 8-2 Design 1 Timing Diagram

This design will also enter a reset condition when the "push-button input" is asserted. The push-button is tied to ground and when pressed will drop the SENSE voltage to 0V, making the device assert a reset. As a good analog practice, a 0.1 µF capacitor was also placed on VDD.

The desired reset timing conditions are sense propagation delay time (tP_HL of 25 μs (how long it takes to assert RESET) and a reset delay time of 40 μs (how long it takes to deassert RESET). Figure 8-3 and Figure 8-4 are the results of the described application where the measured propagation delay and reset delay time are shown respectively.

For the requirement of a maximum output current, an external pull-up resistor needs to be selected so that the current through the external pull-up resistor exceeds no more than 150 µA. When the reset output is low, the voltage drop across the external pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum resistor value. The resistor needs to be greater than 22kΩ in order to pull less than 150 µA in the reset asserted low condition. A resistor value of 30.1kΩ was selected to accomplish this.

Note that this design does not account for tolerances.