SLVSFW1 December   2025 TPS1HC120-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ORing of EN and EN_AUX
      2. 7.3.2 Inductive-Load Switching-Off Clamp
      3. 7.3.3 Full Protections and Diagnostics
        1. 7.3.3.1  Programmable Current Limit
        2. 7.3.3.2  Short-Circuit and Overload Protection
          1. 7.3.3.2.1 Capacitive Charging
        3. 7.3.3.3  On-state Open-Load Detection
        4. 7.3.3.4  Reverse-Polarity and Reverse Battery Protection
        5. 7.3.3.5  Thermal Protection Behavior
        6. 7.3.3.6  UVLO Protection
        7. 7.3.3.7  Loss of GND Protection
        8. 7.3.3.8  Loss of Power Supply Protection
        9. 7.3.3.9  Reverse Current Protection
        10. 7.3.3.10 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Dynamically Changing Current Limit
        2. 8.2.1.2 AEC Q100-012 Test Grade A Certification
        3. 8.2.1.3 EMC Transient Disturbances Test
      2. 8.2.2 Power Dissipation Calculation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Without a GND Network
        2. 8.4.2.2 With a GND Network
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Guidelines

To prevent thermal shutdown, TJ must be less than 150°C. If the output current is very high, the power dissipation may be large. Good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the device.

To achieve good thermal performance, connect the VBB pad to a large copper pour. On the top PCB layer, the pour can extend beyond the package dimensions. In addition to this, having a VBB plane on one or more internal PCB layers and/or on the bottom layer is recommended. Vias must connect these planes to the top VBB pour. Connecting the VOUT pad to a large copper pour on the board can also help to achieve better thermal performance.

If used in the design, the CIC capacitor, must be placed as close as possible to the VBB and GND pins of the device. If a ground network is used for reverse battery protection, the CIC capacitor must be connected from the VBB net to the IC_GND net. The CVBB capacitor must be placed close to the VBB pin and connected to system ground to allow for best performance.

The RILIM resistor must be placed close to the ILIM and GND pins of the device. If a ground network is used for reverse battery protection, the RILIM must be connected from the ILIM pin to the IC_GND net for best current limit performance.