SLVSFY5D April   2022  – February 2026 TPSI3052-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Transmission of the Enable State
      2. 7.3.2 Power Transmission
      3. 7.3.3 Gate Driver
      4. 7.3.4 Modes Overview
      5. 7.3.5 Three-Wire Mode
      6. 7.3.6 Two-Wire Mode
      7. 7.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 7.3.8 Power Supply and EN Sequencing
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 8.2.2.2 Standard Enable, One-Shot Enable
        3. 8.2.2.3 CDIV1, CDIV2 Capacitance
        4. 8.2.2.4 RPXFR Selection
        5. 8.2.2.5 CVDDP Capacitance
        6. 8.2.2.6 Gate Driver Output Resistor
        7. 8.2.2.7 Start-up Time and Recovery Time
        8. 8.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 8.2.2.9 VDDM Ripple Voltage
      3. 8.2.3 Application Curves
      4. 8.2.4 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.6 Gate Driver Output Resistor

The optional external gate driver resistors, RGSRC and RGSNK, along with the diode are used to:

  1. Limit ringing caused by parasitic inductances and capacitances
  2. Limit ringing caused by high voltage switching dv/dt, high current switching di/dt, and body-diode reverse recovery
  3. Fine-tune gate drive strength for sourcing and sinking
  4. Reduce electromagnetic interference (EMI)

The TPSI3052-Q1 has a pullup structure with a P-channel MOSFET with a peak source current of 1.5A. Therefore, the peak source current can be predicted with:

Equation 7. IO+≅min(1.5A, VVDDHRDSON_VDRV+RGSRC+RGFET_INT)

where

  • RGSRC: external turn-on resistance.
  • RDSON_VDRV: TPSI3052-Q1 driver on resistance in high state. See Electrical Characteristics.
  • VVDDH: VDDH voltage. Assumed 15.1V in this example.
  • RGFET_INT: external power transistor internal gate resistance, found in the power transistor data sheet. Assume 0Ω for this example.
  • IO+: peak source current. The minimum value between 1.5A, the gate driver peak source current, and the calculated value based on the gate drive loop resistance.

For this example, RDSON_VDRV = 2.5Ω, RGSRC = 10Ω, and RGFET_INT = 0Ω results in:

Equation 8. I O + ≅ min ( 1 . 5 A , 15 . 1 V 2 . 5 Ω + 10 Ω + 0 Ω ) = 1 . 21 A

Similarly, the TPSI3052-Q1 has a pulldown structure with an N-channel MOSFET with a peak sink current of 3.0A. Therefore, assuming RGFET_INT = 0Ω, the peak sink current can be predicted with:

Equation 9. I O - ≅ min 3 . 0 A , V VDDH × R GSRC + R GSNK - R GSRC × V F × 1 R GSRC × R GSNK + R DSON _ VDRV × ( R GSRC + R GSNK )

where

  • RGSRC: external turn-on resistance.
  • RGSNK: external turn-off resistance.
  • RDSON_VDRV: TPSI3052-Q1 driver on resistance in low state. See Section 5.9.
  • VVDDH: VDDH voltage. Assumed 15.1V in this example.
  • VF: diode forward voltage drop. Assumed 0.7V in this example.
  • IO-: peak sink current. The minimum value between 3.0A, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance.

For this example, assuming RDSON_VDRV = 1.7Ω, RGSRC = 10Ω, RGSNK = 5.0Ω, and RGFET_INT = 0Ω, results in:

Equation 10. I O - ≅ min 3 . 0 A , 15 . 1 V × 10 Ω + 5 Ω - 10 Ω × 0 . 7 V × 1 10 Ω × 5 Ω + 1 . 7 Ω × 10 Ω + 5 Ω = 2 . 91 A

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends to minimize the gate driver loop.