SLVSFY5D April   2022  – February 2026 TPSI3052-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Transmission of the Enable State
      2. 7.3.2 Power Transmission
      3. 7.3.3 Gate Driver
      4. 7.3.4 Modes Overview
      5. 7.3.5 Three-Wire Mode
      6. 7.3.6 Two-Wire Mode
      7. 7.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 7.3.8 Power Supply and EN Sequencing
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 8.2.2.2 Standard Enable, One-Shot Enable
        3. 8.2.2.3 CDIV1, CDIV2 Capacitance
        4. 8.2.2.4 RPXFR Selection
        5. 8.2.2.5 CVDDP Capacitance
        6. 8.2.2.6 Gate Driver Output Resistor
        7. 8.2.2.7 Start-up Time and Recovery Time
        8. 8.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 8.2.2.9 VDDM Ripple Voltage
      3. 8.2.3 Application Curves
      4. 8.2.4 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1 Overview

The TPSI3052-Q1 is a fully integrated, reinforced isolated power switch driver, which when combined with an external power switch, forms a complete isolated Solid State Relay (SSR). With a nominal gate drive voltage of 15V and 1.5/3.0A peak source and sink current, select from a large variety of external power switches to meet a wide range of applications. The TPSI3052-Q1 generates its own secondary supply from the power received from its primary side, so no isolated secondary bias supply is required.

The Functional Block Diagram shows the primary side that includes a transmitter that drives an alternating current into the primary winding of an integrated transformer at a rate determined by the setting of the PXFR pin and the logic state of the EN pin. The transmitter operates at high frequency to drive the transformer to peak efficiency. In addition, the transmitter uses spread spectrum techniques to improve EMI performance, allowing many applications to achieve CISPR 25 - Class 5. During transmission, data information transfers to the secondary side alongside with the power. On the secondary side, the voltage induced on the secondary winding of the transformer is rectified, and the shunt regulator regulates the output voltage level of VDDH. Lastly, the demodulator decodes the received data information and drives VDRV high or low based on the logic state of the EN pin.