SLVSGC5E January   2023  – October 2025 TPS62870 , TPS62871 , TPS62872 , TPS62873

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Range
        2. 7.3.6.2 Output Voltage Setpoint
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Standalone or Primary Device Behavior
        2. 7.3.14.2 Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Inductor
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CC
        6. 9.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8 Register Map

Table 8-1 lists the device registers. Consider all register offset addresses not listed in Table 8-1 as reserved locations. Do not modify the register contents.

Table 8-1 Device Registers
AddressAcronymRegister NameSection
0hVSETOutput Voltage SetpointGo
1hCONTROL1Control 1Go
2hCONTROL2Control 2Go
3hCONTROL3Control 3Go
4hSTATUSStatusGo

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
- nValue after reset or the default value

8.1 VSET Register (Address = 0h) [Reset = X]

VSET is shown in Figure 8-1 and described in Table 8-3.

Return to the Summary Table.

This register controls the output voltage setpoint.

Figure 8-1 VSET Register
76543210
VSET
R/W-X
Table 8-3 VSET Register Field Descriptions
BitFieldTypeResetDescription
7-0VSETR/WX Output voltage setpoint (see the range-setting bits in the CONTROL2 register.)
Range 1: Output voltage setpoint = 0.4V + VSET[7:0] × 1.25mV
Range 2: Output voltage setpoint = 0.4V + VSET[7:0] × 2.5mV
Range 3: Output voltage setpoint = 0.4V + VSET[7:0] × 5mV
Range 4: Output voltage setpoint = 0.8V + VSET[7:0] × 10mV
The state of the VSEL pin during power up determines the reset value.

8.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]

CONTROL1 is shown in Figure 8-2 and described in Table 8-4.

Return to the Summary Table.

This register controls various device configuration options.

Figure 8-2 CONTROL1 Register
76543210
RESETSSCENSWENFPWMENDISCHENHICCUPENVRAMP
R/W-0bR/W-0bR/W-1bR/W-0bR/W-1bR/W-0bR/W-10b
Table 8-4 CONTROL1 Register Field Descriptions
BitFieldTypeResetDescription
7RESETR/W0b Reset device
0b = No effect
1b = Resets all registers to the default values
Reading this bit always returns 0.
6SSCENR/W0b Spread spectrum clocking enable
0b = SSC operation disabled
1b = SSC operation enabled
5SWENR/W1b Software enable
0b = Switching disabled (register values retained)
1b = Switching enabled (without the enable delay)
4FPWMENR/W0b Forced PWM enable
0b = Power-save operation enabled
1b = Forced-PWM operation enabled
This bit is logically ORed with the MODE/SYNC pin. If a high level or a synchronization clock is applied to the MODE/SYNC pin, the device operates in forced-PWM, regardless of the state of this bit.
3DISCHENR/W1b Output discharge enable
0b = Output discharge disabled
1b = Output discharge enabled
2HICCUPENR/W0b Hiccup operation enable
0b = Hiccup operation disabled
1b = Hiccup operation enabled. Do not enable hiccup operation during stacked operation.
1-0VRAMPR/W10b Output voltage ramp speed when changing from one output voltage setting to another
00b = 10mV/µs
01b = 5mV/µs
10b = 1.25mV/µs
11b = 0.5mV/µs

8.3 CONTROL2 Register (Address = 2h) [Reset = 9h]

CONTROL2 is shown in Figure 8-3 and described in Table 8-5.

Return to the Summary Table.

This register controls various device configuration options.

Figure 8-3 CONTROL2 Register
76543210
RESERVEDVRANGESSTIME
R-0000bR/W-10bR/W-01b
Table 8-5 CONTROL2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0000b Reserved for future use. For compatibility with future device variants, program these bits to 0.
3-2VRANGER/W10b Output voltage range
00b = 0.4V to 0.71875V in 1.25mV steps
01b = 0.4V to 1.0375V in 2.5mV steps
10b = 0.4V to 1.675V in 5mV steps
11b = 0.8V to 3.35V in 10mV steps
1-0SSTIMER/W01b Soft-start ramp time
00b = 0.5ms
01b = 1ms
10b = 2ms
11b = 4ms

8.4 CONTROL3 Register (Address = 3h) [Reset = 0h]

CONTROL3 is shown in Figure 8-4 and described in Table 8-6.

Return to the Summary Table.

This register controls various device configuration options.

Figure 8-4 CONTROL3 Register
76543210
RESERVEDSINGLEPGBLNKDVS
R-000000bR/W-0bR/W-0b
Table 8-6 CONTROL3 Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR000000b Reserved for future use. For compatibility with future device variants, program these bits to 0.
1SINGLER/W0b Single operation. This bit controls the internal EN pulldown and SYNC_OUT functions.
0b = EN pin pulldown and SYNC_OUT enabled
1b = EN pin pulldown and SYNC_OUT disabled. Do not use during stacked operation.
0PGBLNKDVSR/W0b Power-good blanking during DVS
0b = PG pin reflects the output of the window comparator.
1b = PG pin is high impedance during DVS.

8.5 STATUS Register (Address = 4h) [Reset = 2h]

STATUS is shown in Figure 8-5 and described in Table 8-7.

Return to the Summary Table.

This register returns the device status flags.

Figure 8-5 STATUS Register
76543210
RESERVEDHICCUPILIMTWARNTSHUTPBUVPBOV
R-00bR-0bR-0bR-0bR-0bR-1bR-0b
Table 8-7 STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00b Reserved for future use. For compatibility with future device variants, ignore these bits.
5HICCUPR0b Hiccup. This bit reports whether a hiccup event occurred since the last time the STATUS register was read.
0b = No hiccup event occurred
1b = A hiccup event occurred
4ILIMR0bCurrent limit. This bit reports whether an current limit event occurred since the last time the STATUS register was read.
0b = No current limit event occurred
1b = An current limit event occurred
3TWARNR0b Thermal warning. This bit reports whether a thermal warning event occurred since the last time the STATUS register was read.
0b = No thermal warning event occurred
1b = A thermal warning event occurred
2TSHUTR0bThermal shutdown. This bit reports whether a thermal shutdown event occurred since the last time the STATUS register was read.
0b = No thermal shutdown event occurred
1b = A thermal shutdown event occurred
1PBUVR1bPower-bad undervoltage. This bit reports whether a power-bad event (output voltage too low) occurred since the last time the STATUS register was read.
0b = No power-bad undervoltage event occurred
1b = A power-bad undervoltage event occurred
0PBOVR0bPower-bad overvoltage. This bit reports whether a power-bad event (output voltage too high) occurred since the last time the STATUS register was read.
0b = No power-bad overvoltage event occurred
1b = A power-bad overvoltage event occurred