SLVSGC5E January   2023  – October 2025 TPS62870 , TPS62871 , TPS62872 , TPS62873

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Range
        2. 7.3.6.2 Output Voltage Setpoint
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Standalone or Primary Device Behavior
        2. 7.3.14.2 Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Inductor
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CC
        6. 9.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from Revision D (September 2025) to Revision E (October 2025)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added TPS62873Z6WRXSR to the Device Options tableGo

Changes from Revision C (January 2025) to Revision D (September 2025)

  • Added links to power-module products, added "Remote Sense" to document title, and added efficiency graphGo
  • Added table note (3) Contact TI for other start-up voltage or I2C address options. Go
  • Updated pin type for SCL pin into I (input) in Table 5-1 Go
  • Added COMP pin voltage and added SDA and EN pin currents in the Absolute Maximum Ratings tableGo
  • Added typical value of Parasitic Input Capacitance for SDA and SCL pins in parameter CIN_SDA_SCL Go
  • Added table note (1) in I2C Timing Characteristics tableGo
  • Changed pin name from SYNCOUT into SYNC_OUT throughout the documentGo
  • Added Equation 1 to clarify ton , changed Equation 2 into IOUT(CCM-DCM), and added Equation 3 for calculating IOUT(PFM-DCM) Go
  • Changed VOUT[7:0] to VSET[7:0]Go
  • Changed CONTROL1 into CONTROL2Go
  • Added TPS6287xZ5 to Table 7-5, and changed VOUT[7:0] to VSET[7:0]Go
  • Added description for EN pin during UVLOGo
  • Added Figure 7-12 Go
  • Updated Table 7-7 by correcting the Vin condition in the 3rd row and adding a sub-row to explain that PG goes low when VOUT > VT+(OVP) or VOUT < VT-(UVP) and DVS inactiveGo
  • Added a description about device setting the PBUV or PBOV bits in case of an undervoltage or overvoltage event, and changed description about the behavior of the PG during DVSGo
  • Added comment to explain that the common power-good signal must to have a pullup to a logic high levelGo
  • Updated description on initialization time interval, and clarified that functions I2C, output discharge, and power good are available after completion of the device initializationGo
  • Deleted the alternative I2C addresses from Table 7-10 Go
  • Updated Figure 7-20 and Figure 7-21 (renamed Target Address into Device Address, and correct the number of bits for Device Address from 8 to 7)Go
  • Changed td(EN) to td(EN)2 Go
  • Added (from 3.8A to 11.3A) to ΔIOUT in Table 9-1 Go
  • Added clarification on IOUT in Equation 11 Go
  • Updated Equation 20 to recalculate the BWinner by using 406μF as max Cout value, and updated Equation 23 based on recalculated BWinner Go
  • Changed value of optional CC2 from 1pF to 10pFGo
  • Added comment that all curves are obtained with L = 110nH (Coilcraft XGL4020-111ME) and fsw = 2.25MHz, unless noted otherwiseGo