SLVSGE8B November   2022  – August 2024 TPS35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Supervisor
      2. 7.3.2 Timeout Watchdog Timer
        1. 7.3.2.1 tWD Timer
        2. 7.3.2.2 Watchdog Enable Disable Operation
        3. 7.3.2.3 tSD Watchdog Start Up Delay
        4. 7.3.2.4 SET Pin Behavior
      3. 7.3.3 Manual RESET
      4. 7.3.4 RESET and WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed watchdog Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed watchdog Timing
        2. 8.1.2.2 Adjustable Capacitor Timings
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Voltage Threshold
          2. 8.2.1.2.2 Meeting the Watchdog Timeout Period
          3. 8.2.1.2.3 Setting the Reset Delay
          4. 8.2.1.2.4 Setting the Startup Delay and Output Topology
          5. 8.2.1.2.5 Calculating the RESET Pullup Resistor
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

At 1.04V ≤ VDD ≤ 6V, MR = Open, RESET pull-up resistor (Rpull-up) = 100kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100kΩ to VDD, output RESET / WDO load (CLOAD) = 10pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tGI_VIT– Glitch immunity VIT–
5% VIT– overdrive(1)		 15 µs
tMR_PW MR pin pulse duration to assert reset 100 ns
tP-WD WDI pulse duration to start next frame (2) VDD > VIT– 500 ns
tHD-WDEN WD-EN hold time to enable or disable WD operation (2) VDD > VIT– 200 µs
tHD-SETx SETx hold time to change WD timer setting (2) VDD > VIT– 150 µs
tWD Watchdog timeout period Orderable Option TPS35xxxxB 0.8 1 1.2 ms
Orderable Option TPS35xxxxC 4 5 6
Orderable Option TPS35xxxxD 9 10 11
Orderable Option TPS35xxxxE 18 20 22
Orderable Option TPS35xxxxF 45 50 55
Orderable Option TPS35xxxxG 90 100 110
Orderable Option TPS35xxxxH 180 200 220
Orderable Option TPS35xxxxI 0.9 1 1.1 s
Orderable Option TPS35xxxxJ 1.26 1.4 1.54
Orderable Option TPS35xxxxK 1.44 1.6 1.76
Orderable Option TPS35xxxxL 9 10 11
Orderable Option TPS35xxxxM 45 50 55
Orderable Option TPS35xxxxN 90 100 110
(1) Overdrive % = [(VDD/ VIT–) – 1] × 100%
(2) Not production tested