SLVSH94 May   2026 TPS26742-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Recommended Capacitance
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Power Path Supervisory Characteristics
    9. 6.9  CC Cable Detection Characteristics
    10. 6.10 Legacy Charging Characteristics
    11. 6.11 Px_VCONN Switch Characteristics
    12. 6.12 CC PHY Characteristics
    13. 6.13 Thermal Shutdown Characteristics
    14. 6.14 Oscillator Characteristics
    15. 6.15 ADC Characteristics
    16. 6.16 Liquid Detection Characteristics
    17. 6.17 Input/Output (I/O) Characteristics (P0_GPIOx)
    18. 6.18 Input/Output (I/O) Characteristics (P1_GPOx)
    19. 6.19 I2C Requirements and Characteristics
    20. 6.20 UART
    21. 6.21 SYNC output
    22. 6.22 PWM Timer
    23. 6.23 Flash Memory Characteristics
    24. 6.24 Boot Timing
    25. 6.25 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
        1. 8.3.1.1 Power-On and Supervisory Functions
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a Source
      3. 8.3.3  VCONN Power Path
        1. 8.3.3.1 Current Clamp
        2. 8.3.3.2 Px_VCONN Local Overtemperature Shut Down (OTSD)
        3. 8.3.3.3 Px_VCONN OVP
        4. 8.3.3.4 Px_VCONN UVLO
        5. 8.3.3.5 Px_VCONN RCP
      4. 8.3.4  USB-PD Physical Layer
        1. 8.3.4.1 USB-PD Encoding and Signaling
        2. 8.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.4.3 USB-PD BMC Transmitter
        4. 8.3.4.4 USB-PD BMC Receiver
        5. 8.3.4.5 Squelch Receiver
      5. 8.3.5  DBG_SDA, DBG_SCL and DP/DM Overview
        1. 8.3.5.1 Closed Chassis Debugging and Updating Flash
          1. 8.3.5.1.1 I2C4 Access For Closed-chassis Debugging
          2. 8.3.5.1.2 UART Access for Closed-chassis Debugging
        2. 8.3.5.2 BC1.2 and Legacy Charging Functionality
          1. 8.3.5.2.1 Charging Downstream Port (CDP) Mode
          2. 8.3.5.2.2 Dedicated Charging Port (DCP) Mode
      6. 8.3.6  Liquid Detection
      7. 8.3.7  Local Interconnect Network (LIN) Support
      8. 8.3.8  Thermal Shutdown
      9. 8.3.9  ADC
        1. 8.3.9.1 ADC Divider Ratios
      10. 8.3.10 VIN Power Foldback
      11. 8.3.11 Thermal Foldback
      12. 8.3.12 DisplayPort Hot-Plug Detect (HPD)
      13. 8.3.13 General GPIO
        1. 8.3.13.1 P0_GPIOx
        2. 8.3.13.2 P1_GPOx
      14. 8.3.14 ENSD Functionality
      15. 8.3.15 Px_SYNC Output
      16. 8.3.16 Pulse-Width Modulation (PWM) Output
      17. 8.3.17 I2C Interface
        1. 8.3.17.1 I2C Interface Hardware
        2. 8.3.17.2 I2C Interface Description
        3. 8.3.17.3 I2C Clock Stretching
        4. 8.3.17.4 Unique Address Interface
        5. 8.3.17.5 I2C Address Setting
      18. 8.3.18 System Power Management (SPM) Across Ports
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Strapping to Configure Default Behavior (CONFIG)
      2. 8.4.2 Power States
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 CC Pin Recommendations
        2. 9.2.1.2 TI Firmware Update (TFU)
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Dual-Port SPR Charger
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Input Power Supply
      2. 9.4.2 5V Power Supply
      3. 9.4.3 3.3V Power Supply
      4. 9.4.4 1.35V Power Supply
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.17.2 I2C Interface Description

The TPS26742-Q1 supports Standard, Fast mode, and Fast-mode, plus I2C interfaces. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines are required to connect to a supply through a pull-up resistor.

Figure 8-29 shows the start and stop conditions of the transfer. Figure 8-30 shows the SDA and SCL signals for transferring a bit. Figure 8-31 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

TPS26742-Q1 I2C Definition of Start and Stop Conditions Figure 8-29 I2C Definition of Start and Stop Conditions
TPS26742-Q1 I2C Bit Transfer Figure 8-30 I2C Bit Transfer
TPS26742-Q1 I2C Acknowledgment Figure 8-31 I2C Acknowledgment