SLVSHC7B December   2023  – September 2025 DRV8334

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions 48-Pin DRV8334
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings DRV8334
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 3x PWM Mode with SPI enable control
          4. 6.3.1.1.4 1x PWM Mode
          5. 6.3.1.1.5 SPI Gate Drive Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 GVDD Charge pump/LDO
          3. 6.3.1.2.3 VCP Trickle Charge pump
          4. 6.3.1.2.4 Gate Driver Output
          5. 6.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 6.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 6.3.1.2.7 Propagation Delay
          8. 6.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 Low-Side Current Sense Amplifiers
        1. 6.3.2.1 Unidirectional Current Sense Operation
        2. 6.3.2.2 Bidirectional Current Sense Operation
      3. 6.3.3 Gate Driver Shutdown
        1. 6.3.3.1 DRVOFF Gate Driver Shutdown
        2. 6.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 6.3.4 Gate Driver Protective Circuits
        1. 6.3.4.1  PVDD Supply Undervoltage Warning (PVDD_UVW)
        2. 6.3.4.2  PVDD Supply Undervoltage Lockout (PVDD_UV)
        3. 6.3.4.3  PVDD Supply Overvoltage Fault (PVDD_OV)
        4. 6.3.4.4  GVDD Undervoltage Lockout (GVDD_UV)
        5. 6.3.4.5  GVDD Overvoltage Fault (GVDD_OV)
        6. 6.3.4.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.4.7  BST Overvoltage Fault (BST_OV)
        8. 6.3.4.8  VCP Undervoltage Fault (CP_OV)
        9. 6.3.4.9  VCP Overvoltage Fault (CP_OV)
        10. 6.3.4.10 VDRAIN Undervoltage Fault (VDRAIN_UV)
        11. 6.3.4.11 VDRAIN Overvoltage Fault (VDRAIN_OV)
        12. 6.3.4.12 MOSFET VGS Monitoring Protection
        13. 6.3.4.13 MOSFET VDS Overcurrent Protection (VDS_OCP)
        14. 6.3.4.14 VSENSE Overcurrent Protection (SEN_OCP)
        15. 6.3.4.15 Phase Comparators
        16. 6.3.4.16 Thermal Shutdown (OTSD)
        17. 6.3.4.17 Thermal Warning (OTW)
        18. 6.3.4.18 OTP CRC
        19. 6.3.4.19 SPI Watchdog Timer
        20. 6.3.4.20 Phase Diagnostic
    4. 6.4 Device Functional Modes
      1. 6.4.1 Gate Driver Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Operating Mode
      2. 6.4.2 Device Power Up Sequence
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 SPI Format
      3. 6.5.3 SPI Format Diagrams
  8. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

6.4.2 Device Power Up Sequence

DRV8334 Device Power Up Sequence and tWAKE Figure 6-23 Device Power Up Sequence and tWAKE

Figure 6-23 explains the device power up sequence including the device internal information. As described in Section 6.4, if the nSLEEP pin is driven high, the device starts the power up sequence to enable the internal LDOs, GVDD and VCP charge pump. The nFAULT output is low when the device completes the power up sequence and enters the Operating Mode. The external MCU additonaly waits for the pre-charge of bootstrap capacitors before toggling the high-side gate drivers, and the SPI status flag BST_UVx can be used to check the status of pre-charge operation.