SLVSHF5 November   2024 TLC6989

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Oscillator and Clocks
        1. 7.3.1.1 System Clock
        2. 7.3.1.2 Continuous Clock Serial Interface (CCSI) Clock
      2. 7.3.2 Continuous Clock Serial Interface (CCSI)
        1. 7.3.2.1 Command Format
        2. 7.3.2.2 Command Recognition and Synchronization
        3. 7.3.2.3 CCSI Command Queue
        4. 7.3.2.4 CCSI Start Bit and Check Bits Insertion and Removal
      3. 7.3.3 FIFO
        1. 7.3.3.1 FIFO level and Data Ready (DRDY) Interrupt
        2. 7.3.3.2 FIFO Clearance
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  Undervoltage Lockout
        2. 7.3.4.2  Oscillator Fault Diagnostics
        3. 7.3.4.3  SPI Communications Loss
        4. 7.3.4.4  SPI Communications Error
          1. 7.3.4.4.1 Reset Timer
          2. 7.3.4.4.2 Chip Select (CS) Reset
          3. 7.3.4.4.3 CRC Error
          4. 7.3.4.4.4 Register write failure
        5. 7.3.4.5  CCSI Communications Loss
          1. 7.3.4.5.1 SIN Stuck-at Diagnostics
        6. 7.3.4.6  CCSI Communications Error
          1. 7.3.4.6.1 CHECK Bit Error
          2. 7.3.4.6.2 Data Integrity Diagnostics
          3. 7.3.4.6.3 CCSI Command Queue Overflow
        7. 7.3.4.7  FIFO Diagnostics
          1. 7.3.4.7.1 TXFIFO Overflow
          2. 7.3.4.7.2 TXFIFO Underflow
          3. 7.3.4.7.3 TXFIFO Single Error Detection (SED)
          4. 7.3.4.7.4 RXFIFO Overflow
          5. 7.3.4.7.5 RXFIFO Underflow
          6. 7.3.4.7.6 RXFIFO Single Error Detection (SED)
        8. 7.3.4.8  OTP CRC Error
        9. 7.3.4.9  Fault Masking
        10. 7.3.4.10 Diagnostics Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unpowered
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Failsafe State
    5. 7.5 Programming
      1. 7.5.1 SPI Data Validity
      2. 7.5.2 Chip Select (CS) and SPI Reset Control
      3. 7.5.3 SPI Command Format
      4. 7.5.4 SPI Command Detail
    6. 7.6 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.3 FIFO

The TLC6989 has both a transmit and receive FIFO. The naming of the FIFOs are viewed from the Continuous Clock Serial Interface (CCSI). That means the transmit FIFO (TXFIFO) is the data that was received by the SPI peripheral and transmitted by the CCSI controller. The receive FIFO (RXFIFO) is the data received by the CCSI peripheral which can be read by the controller via SPI peripheral.

Both FIFOs are 16-bit-wide first-in-first-out memory buffers. The FIFOs are used to store data words to fullfil the timing requirements while the data is crossing between the SPI clock domain and CCSI clock domain. The TXFIFO holds the data during the crossover from the SPI clock to the CCSI clock domain. The RXFIFO holds the data during the crossover from the CCSI clock domain to the SPI clock domain.

When the SPI clock domain runs at a higher frequency than the CCSI clock domain, the TXFIFO stores data already received by the SPI peripheral which has not been transmitted yet by the CCSI controller. A counter (TXFFST) keeps track of the number of words currently stored in the TXFIFO. The example where the SPI peripheral runs at a higher clock frequency than the CCSI controller is depicted in Figure 7-5. Note that in this figure every data word is 16 bits. That means that when the width of the block is larger, the clock frequency is lower.

TLC6989 Example of SPI peripheral running at higher frequency than CCSI controller Figure 7-5 Example of SPI peripheral running at higher frequency than CCSI controller

When the SPI peripheral runs at a lower clock frequency than the CCSI controller, the TXFIFO is used to first store a number of data words received by the SPI peripheral before the transmission by the CCSI controller starts. Following this method, the data stream on the CCSI can be made continuous without requiring the continuous clock to stop because the data word was not received yet by the SPI peripheral. An example of this situation is depicted in Figure 7-6.

TLC6989 Example of SPI peripheral running at lower frequency than CCSI controller Figure 7-6 Example of SPI peripheral running at lower frequency than CCSI controller

For the RXFIFO, the CCSI peripheral receives the data and stores them on the RXFIFO. The SPI peripheral reads the data from the RXFIFO and transmits them to the SPI controller. Also for the RXFIFO a counter (RXFFST) exists to keep track of the number of data words currently stored.

Note that when an END byte is received, the storage stops. The END byte itself is not stored on the RXFIFO. Also the START bit and CHECK bits are not stored.