SLVSHI5A April   2024  – May 2025 TPS23881B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Detailed Pin Description
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Operating Modes
        1. 8.1.1.1 Auto
        2. 8.1.1.2 Autonomous
        3. 8.1.1.3 Semiauto
        4. 8.1.1.4 Manual and Diagnostic
        5. 8.1.1.5 Power Off
      2. 8.1.2 PoE Compliance Terminology
      3. 8.1.3 Channel versus Port Terminology
      4. 8.1.4 Requested Class versus Assigned Class
      5. 8.1.5 Power Allocation and Power Demotion
      6. 8.1.6 Programmable SRAM
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 Analog-to-Digital Converters (ADC)
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Current Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Detection
      2. 8.4.2 Connection Check
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 I2C Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 Complete Register Set
      2. 8.6.2 Detailed Register Descriptions
        1. 8.6.2.1  INTERRUPT Register
        2. 8.6.2.2  INTERRUPT MASK Register
        3. 8.6.2.3  POWER EVENT Register
        4. 8.6.2.4  DETECTION EVENT Register
        5. 8.6.2.5  FAULT EVENT Register
        6. 8.6.2.6  START/ILIM EVENT Register
        7. 8.6.2.7  SUPPLY and FAULT EVENT Register
          1. 8.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 8.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 8.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 8.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 8.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 8.6.2.12 POWER STATUS Register
        13. 8.6.2.13 PIN STATUS Register
          1. 8.6.2.13.1 AUTONOMOUS MODE
        14. 8.6.2.14 OPERATING MODE Register
        15. 8.6.2.15 DISCONNECT ENABLE Register
        16. 8.6.2.16 DETECT/CLASS ENABLE Register
        17. 8.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 8.6.2.18 TIMING CONFIGURATION Register
        19. 8.6.2.19 GENERAL MASK Register
        20. 8.6.2.20 DETECT/CLASS RESTART Register
        21. 8.6.2.21 POWER ENABLE Register
        22. 8.6.2.22 RESET Register
        23. 8.6.2.23 ID Register
        24. 8.6.2.24 Connection Check and Auto Class Status Register
        25. 8.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 8.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 8.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 8.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 8.6.2.29 Capacitance (Legacy PD) Detection
        30. 8.6.2.30 Power-on Fault Register
        31. 8.6.2.31 PORT RE-MAPPING Register
        32. 8.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 8.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 8.6.2.34 4-Pair Wired and Port Power Allocation Register
        35. 8.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 8.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
        37. 8.6.2.37 TEMPERATURE Register
        38. 8.6.2.38 4-Pair Fault Configuration Register
        39. 8.6.2.39 INPUT VOLTAGE Register
        40. 8.6.2.40 CHANNEL 1 CURRENT Register
        41. 8.6.2.41 CHANNEL 2 CURRENT Register
        42. 8.6.2.42 CHANNEL 3 CURRENT Register
        43. 8.6.2.43 CHANNEL 4 CURRENT Register
        44. 8.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 8.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 8.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 8.6.2.47 CHANNEL 4 VOLTAGE Register
        48. 8.6.2.48 2x FOLDBACK SELECTION Register
        49. 8.6.2.49 FIRMWARE REVISION Register
        50. 8.6.2.50 I2C WATCHDOG Register
        51. 8.6.2.51 DEVICE ID Register
        52. 8.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 8.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 8.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 8.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
        56. 8.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 8.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 8.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 8.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
        60. 8.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 8.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 8.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 8.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
        64. 8.6.2.64 AUTO CLASS CONTROL Register
        65. 8.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 8.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 8.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 8.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
        69. 8.6.2.69 ALTERNATIVE FOLDBACK Register
        70. 8.6.2.70 SRAM CONTROL Register
          1. 8.6.2.70.1 SRAM START ADDRESS (LSB) Register
          2. 8.6.2.70.2 SRAM START ADDRESS (MSB) Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
        1. 9.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Connections on Unused Channels
        2. 9.2.2.2 Power Pin Bypass Capacitors
        3. 9.2.2.3 Per Port Components
        4. 9.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 VDD
      2. 9.3.2 VPWR
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Kelvin Current Sensing Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Component Placement and Routing Guidelines
          1. 9.4.2.1.1 Power Pin Bypass Capacitors
          2. 9.4.2.1.2 Per-Port Components
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.6.1 Complete Register Set

Table 8-4 Main Registers
Cmd CodeRegister or
Command Name		I2C
R/W		Data
Byte		RST StateBits Description
INTERRUPTS
00hINTERRUPTRO11000,0000b(1)SUPFSTRTFIFAULTCLASCDETCDISFPGCPEC
01hINTERRUPT MASKR/W11000,0000b
SUMSKSTMSKIFMSKCLMSKDEMSKDIMSKPGMSKPEMSK
EVENT
02hPOWER EVENTRO10000,0000bPower Good status changePower Enable status change
03hCoR1PGC4PGC3PGC2PGC1PEC4PEC3PEC2PEC1
04hDETECTION EVENTRO10000,0000bClassificationDetection
05hCoR1CLSC4CLSC3CLSC2CLSC1DETC4DETC3DETC2DETC1
06hFAULT EVENTRO10000,0000bDisconnect occurredPCUT fault occurred
07hCoR1DISF4DISF3DISF2DISF1PCUT4PCUT3PCUT2PCUT1
08hSTART/ILIM EVENTRO10000,0000bILIM fault occurredSTART fault occurred
09hCoR1ILIM4ILIM3ILIM2ILIM1STRT4STRT3STRT2STRT1
0AhSUPPLY/FAULT EVENTRO10111,0000b(2)TSDVDUVVDWRNVPUVPCUT34PCUT12OSSERAMFLT
0BhCoR1
STATUS
0ChCHANNEL 1 DISCOVERYRO10000,0000bRequested CLASS Channel 1DETECT Channel 1
0DhCHANNEL 2 DISCOVERYRO10000,0000bRequested CLASS Channel 2DETECT Channel 2
0EhCHANNEL 3 DISCOVERYRO10000,0000bRequested CLASS Channel 3DETECT Channel 3
0FhCHANNEL 4 DISCOVERYRO10000,0000bRequested CLASS Channel 4DETECT Channel 4
10hPOWER STATUSRO10000,0000bPG4PG3PG2PG1PE4PE3PE2PE1
11hPIN STATUSRO10,A[4:0],0,0RsvdSLA4SLA3SLA2SLA1SLA0RsvdRsvd
CONFIGURATION
12hOPERATING MODER/W10000,0000bChannel 4 ModeChannel 3 ModeChannel 2 ModeChannel 1 Mode
13hDISCONNECT ENABLER/W10000 ,1111bRsvdRsvdRsvdRsvdDCDE4DCDE3DCDE2DCDE1
14hDETECT/CLASS ENABLER/W10000,0000bCLE4CLE3CLE2CLE1DETE4DETE3DETE2DETE1
15hPWRPR/PCUT DISABLER/W10000,0000bOSS4OSS3OSS2OSS1DCUT4DCUT3DCUT2DCUT1
16hTIMING CONFIGR/W10000,0000bTLIMTSTARTTOVLDTMPDO
17hGENERAL MASKR/W11000,0000bINTENRsvdnbitACCMbitPrtyCLCHEDECHERsvd
PUSH BUTTONS
18hDETECT/CLASS RestartWO10000,0000bRCL4RCL3RCL2RCL1RDET4RDET3RDET2RDET1
19hPOWER ENABLEWO10000,0000bPOFF4POFF3POFF2POFF1PWON4PWON3PWON2PWON1
1AhRESETWO10000,0000bCLRAINCLINPRsvdRESALRESP4RESP3RESP2RESP1
GENERAL/SPECIALIZED
1BhIDRO10101,0101bMFR IDIC Version
1ChAUTOCLASS and CONNECTION CHECKRO10000,0000bAC4AC3AC2AC1CC34_2CC34_1CC12_2CC12_1
1DhRESERVEDR/W10000,0000bRsrvd
1Eh2P POLICE 1 CONFIGR/W11111,1111b2-Pair POLICE Channel 1
1Fh2P POLICE 2 CONFIGR/W11111,1111b2-Pair POLICE Channel 2
20h2P POLICE 3 CONFIGR/W11111,1111b2-Pair POLICE Channel 3
21h2P POLICE 4CONFIGR/W11111,1111b2-Pair POLICE Channel 4
22hCAP MEASUREMENT(3)R/W10000,0000bRsvdCDET4RsvdCDET3RsvdCDET2RsvdCDET1
23hReservedR/W10000,0000bRsvdRsvdRsvdRsvdRsvdRsvdRsvdRsvd
24hPower-on FAULTRO10000,0000bPF Channel 4PF Channel 3PF Channel 2PF Channel 1
25hCoR1
26hRE-MAPPINGR/W11110,0100bPhysical re-map Logical Port 4Physical re-map Logical Port 3Physical re-map Logical Port 2Physical re-map Logical Port 1
27hMulti-Bit Priority 21R/W10000,0000bRsvdChannel 2RsvdChannel 1
28hMulti-Bit Priority 43R/W10000,0000bRsvdChannel 4RsvdChannel 3
29hPort Power AllocationR/W10000,0000b4P34MC344P12MC12
2Ah4P POLICE 12 CONFIGR/W11111,1111b4-Pair POLICE Channels 1 and 2
2Bh4P POLICE 34 CONFIGR/W11111,1111b4-Pair POLICE Channels 3 and 4
2ChTEMPERATURERO10000,0000bTemperature (bits 7 to 0)
2Dh4P FAULT CONFIGR/W10000,0000bNLM34NLM12NCT34NCT124PPCT344PPCT12DCDT34DCDT12
2EhINPUT VOLTAGERO20000,0000bInput Voltage: LSByte
2FhRO0000,0000bRsvdRsvdInput Voltage: MSByte (bits 13 to 8)
EXTENDED REGISTER SET – PARAMETRIC MEASUREMENT
30hChannel 1 CURRENTRO20000,0000bChannel 1 Current: LSByte
31hRO0000,0000bRsvdRsvdChannel 1 Current: MSByte (bits 13 to 8)
32hChannel 1 VOLTAGERO20000,0000bChannel 1 Voltage: LSByte
33hRO0000,0000bRsvdRsvdChannel 1 Voltage: MSByte (bits 13 to 8)
(1) SUPF bit reset state shown is at Power up only
(2) VDUV, VPUV and VDWRN bits reset state shown is at Power up only
(3) Capacitance Measurement is only supported if SRAM code is programmed
Table 8-5 Main Registers
Cmd Code Register or
Command Name		 I2C R/W Data Byte RST State Bits Description
34h Channel 2 CURRENT RO 2 0000,0000b Channel 2 Current: LSByte
35h RO 0000,0000b Rsvd Rsvd Channel 2 Current: MSByte (bits 13 to 8)
36h Channel 2 VOLTAGE RO 2 0000,0000b Channel 2 Voltage: LSByte
37h RO 0000,0000b Rsvd Rsvd Channel 2 Voltage: MSByte (bits 13 to 8)
38h Channel 3 CURRENT RO 2 0000,0000b Channel 3 current: LSByte
39h RO 0000,0000b Rsvd Rsvd Channel 3 Current: MSByte (bits 13 to 8)
3Ah Channel 3 VOLTAGE RO 2 0000,0000b Channel 3 Voltage: LSByte
3Bh RO 0000,0000b Rsvd Rsvd Channel 3 Voltage: MSByte (bits 13 to 8)
3Ch Channel 4 CURRENT RO 2 0000,0000b Channel 4 current: LSByte
3Dh RO 0000,0000b Rsvd Rsvd Channel 4 Current: MSByte (bits 13 to 8)
3Eh Channel 4 VOLTAGE RO 2 0000,0000b Channel 4 Voltage: LSByte
3Fh RO 0000,0000b Rsvd Rsvd Channel 4 Voltage: MSByte (bits 13 to 8)
CONFIGURATION/OTHERS
41h FIRMWARE REVISION RO 1 RRRR,RRRRb Firmware Revision
42h I2C WATCHDOG R/W 1 0001,0110b Rsvd Rsvd Rsvd Watchdog Disable WDS
43h DEVICE ID RO 1 0010,0100b Device ID number Silicon Revision number
SIGNATURE MEASUREMENTS
44h Ch1 DETECT RESISTANCE RO 1 0000,0000b Channel 1 Resistance
45h Ch2 DETECT RESISTANCE RO 1 0000,0000b Channel 2 Resistance
46h Ch3 DETECT RESISTANCE RO 1 0000,0000b Channel 3 Resistance
47h Ch4 DETECT RESISTANCE RO 1 0000,0000b Channel 4 Resistance
48h Ch1 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 1 Capacitance
49h Ch2 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 2 Capacitance
4Ah Ch3 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 3 Capacitance
4Bh Ch4 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 4 Capacitance
ASSIGNED CHANNEL STATUS
4Ch ASSIGNED CLASS CHANNEL 1 RO 1 0000,0000b Assigned CLASS Channel 1 Previous CLASS Channel 1
4Dh ASSIGNED CLASS CHANNEL 2 RO 1 0000,0000b Assigned CLASS Channel 2 Previous CLASS Channel 2
4Eh ASSIGNED CLASS CHANNEL 3 RO 1 0000,0000b Assigned CLASS Channel 3 Previous CLASS Channel 3
4Fh ASSIGNED CLASS CHANNEL 4 RO 1 0000,0000b Assigned CLASS Channel 4 Previous CLASS Channel 4
AUTOCLASS CONFIGURATION/MEASUREMENTS
50h AUTOCLASS CONTROL R/W 1 0000,0000b MAC4 MAC3 MAC2 MAC1 AAC4 AAC3 AAC2 AAC1
51h CHANNEL 1 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 1 AutoClass Power
52h CHANNEL 2 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 2 AutoClass Power
53h CHANNEL 3 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 3 AutoClass Power
54h CHANNEL 4 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 4 AutoClass Power
MISCELLANEOUS
55h ALTERNATIVE FOLDBACK R/W 1 0000,0000b ALTFB4 ALTFB3 ALTFB2 ALTFB1 ALTIR4 ALTIR3 ALTIR2 ALTIR1
56h - 5Fh RESERVED R/W 1 0000,0000b Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd
SRAM
60h SRAM CONTROL R/W 1 0000,0000b PROG_SEL CPU_RST Rsrvd PAR_EN RAM_EN PAR_SEL RZ/W CLR_PTR
61h SRAM DATA R/W - - SRAM DATA - Read and Write (continuous)
62h START ADDRESS R/W 1 0000,0000b Programming Start Address (LSB)
63h R/W 1 0000,0000b Programming Start Address (MSB)
64h - 6Fh RESERVED R/W 1 0000,0000b Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd