SLVSHL6A June   2025  – December 2025 TPSI2260-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure - Chassis Ground Reference
      4. 9.2.4 Application Performance Plot
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.9 Electrical Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values are measured at TJ = 25°C, VVDD = 5 V, VEN = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PRIMARY SIDE SUPPLY (VDD)
VUVLO VDD undervoltage threshold VDD rising

 4.1 4.3 4.5 V
VDD falling 4.0 4.2 4.45 V
Hysteresis 40 100 150 mV
IVDD_ON VDD current, device powered on  VEN = 5 V, TJ = 25°C 5 11 mA
 VEN = 5 V, –40°C ≤ TJ ≤ 150°C 5 12 mA
IVDD_OFF VDD current, 5 V, device powered off VVDD = 5 V, VEN = 0 V, TJ = 25°C 4 8 µA
VVDD = 5 V, VEN = 0 V, TJ = 105°C 6.3 11 µA
VVDD = 5 V, VEN = 0 V, TJ = 125°C 7.6 16 µA
VVDD = 5 V, VEN = 0 V,  –40°C ≤ TJ ≤ 150°C 30 µA
VDD current, 20 V, device powered off VVDD = 20 V, VEN = 0, V TJ = 25°C 9.2 10.5 µA
VVDD = 20 V, VEN = 0 V, TJ = 105°C 13 17
VVDD = 20 V, VEN = 0 V, TJ = 125°C 15 25
VVDD = 20 V, VEN = 0 V, –40°C ≤ TJ ≤ 150°C 40
FET CHARACTERISTICS (S1, S2)
RDSON On resistance IO = 2 mA, TJ = 25°C 65 88 Ω
IO = 2 mA, TJ = 85°C 88 120
IO = 2 mA, TJ = 105°C 96 125
IO = 2 mA, TJ = 125°C 105 140
IO = 2 mA, –40°C ≤ TJ ≤ 150°C 150
IOFF Off leakage, 600 V V = +/–600 V, TJ = 25°C 0.058 0.25 µA
V = +/–600 V, TJ = 85°C 0.5
V = +/–600V, TJ = 105°C 1.5
V = +/–600 V, TJ = 125°C 6
V = +/–600V, –40°C ≤ TJ ≤ 150°C 50
Off leakage, 500 V V = +/–500V, TJ = 25°C 0.055 0.25 µA
V = +/–500V, TJ = 85°C 0.43
V = +/–500V, TJ = 105°C 1.22
V = +/–500V, TJ = 125°C 5.75
V = +/–500V, –40°C ≤ TJ ≤ 150°C 44
VAVA Avalanche voltage IO = 10 µA, TJ = 25°C 650 770 V
IO = 100 µA, TJ = 150°C 650 770
COSS S1, S2 capacitance VS1,S2 = 0 V, SM float, F = 1 MHz 188 pF
TTAP1
Thermal Avalanche Protection threshold
 		 Assertion 155 C
TTAP_END
Thermal Avalanche Protection threshold
 		 De-assertion 85 125 C
LOGIC-LEVEL INPUT (EN
VIL Input logic low voltage 0.0 0.8 V
VIH Input logic high voltage 2.1 20.0 V
VHYS Input logic hysteresis 100 250 300 mV
IIL Input logic low current VEN = 0 V –0.1 0.1 µA
VEN = 0.8 V 0.1 0.68 1.8 µA
IIH Input logic high current VEN = 10 V 6.0 13.5 30 µA
IIH Input logic high current VEN = 5 V 1.5 4.5 12 µA
VEN = 20 V 15 32 65 µA
IVDD_FS VDD fail-safe current VEN = 20 V, VVDD = 0 V –0.1 0 0.1 µA
RPD Pulldown resistance Two point measurement, VEN = 0.5 V and VEN = 0.8 V 550 1180 2100 kΩ
NOISE IMMUNITY
CMTI Common-mode transient immunity |VCM| = 500V 100 V/ns