SLVSHQ3 December   2025 DRV8363

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8363
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information 1pkg
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 1x PWM Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_OV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Phase Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
    7. 6.7 Register Maps
      1. 6.7.1 STATUS Registers
      2. 6.7.2 CONTROL Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application with 48-pin package
        1. 7.2.1.1 External Components
      2. 7.2.2 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information

6.7.1 STATUS Registers

Table 6-10 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 6-10 should be considered as reserved locations and the register contents should not be modified.

Table 6-10 STATUS Registers
OffsetAcronymDescriptionSection
0hIC_STAT1IC Status Register 1Section 6.7.1.1
1hIC_STAT2IC Status Register 2Section 6.7.1.2
2hIC_STAT3IC Status Register 3Section 6.7.1.3
3hIC_STAT4IC Status Register 4Section 6.7.1.4
4hIC_STAT5IC Status Register 5Section 6.7.1.5
5hIC_STAT6IC Status Register 6Section 6.7.1.6

Complex bit access types are encoded to fit into small table cells. Table 6-11 shows the codes that are used for access types in this section.

Table 6-11 STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

6.7.1.1 IC_STAT1 Register (Offset = 0h) [Reset = 8080h]

IC_STAT1 is shown in Table 6-12.

Return to the Summary Table.

Table 6-12 IC_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15SPI_OKR1h No SPI Fault is detected
  • 0h = SPI Fault is detected
  • 1h = No fault
14FAULTR0h Logic OR of FAULT status registers. Inverse mirror of nFAULT pin.
  • 0h = nFAULT pin is high. No fault events detected.
  • 1h = nFAULT pin is low. One or multiple fault events detected.
13WARNR0h Logic OR of WARN status, except OTW
  • 0h = No warning event detected
  • 1h = One or multiple warning event detected
12VDSR0h Logic OR of VDS overcurrent detection
  • 0h = No VDS events detected.
  • 1h = One or multiple VDS events detected.
11VGSR0h Logic OR of VGS detection
  • 0h = No VGS events detected.
  • 1h = One or multiple VGS events detected.
10SNS_OCPR0h Logic OR of Sense overcurrent detection
  • 0h = No sense overcurrent events detected.
  • 1h = One or multiple sense overcurrent events detected.
9OVR0h Logic OR of supply voltage overvoltage detection
  • 0h = No overvoltage events detected.
  • 1h = One ore more overvoltage events detected.
8UVR0h Logic OR of supply voltage undervoltage detection
  • 0h = No undervoltage events detected.
  • 1h = One ore more undervoltage events detected.
7RESET_STATR1h Digital reset status: follows digital reset signal. Cleared by setting CLR_FLT=1.
  • 0h = Signal has been cleared by setting CLR_FLT to 1
  • 1h = Digital has come out from reset
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2RESERVEDR0h Reserved
1OTWR0h Overtemperature Warning Status Bit
  • 0h = No event is detected
  • 1h = Overtemperature warning event detected
0DRV_STATR0h Indicates Driver Enable Status: driver is following INxx inputs. Status will start as 0b, but will self-set to 1b at completion of power-up sequence.
  • 0h = Driver output is disabled
  • 1h = Driver output is enabled

6.7.1.2 IC_STAT2 Register (Offset = 1h) [Reset = 0000h]

IC_STAT2 is shown in Table 6-13.

Return to the Summary Table.

Table 6-13 IC_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10SNS_OCP_AR0h Overcurrent on External Sense Resistor Status Bit on phase A
  • 0h = No fault detected
  • 1h = Fault detected
9SNS_OCP_BR0h Overcurrent on External Sense Resistor Status Bit on phase B
  • 0h = No fault detected
  • 1h = Fault detected
8SNS_OCP_CR0h Overcurrent on External Sense Resistor Status Bit on phase C
  • 0h = No fault detected
  • 1h = Fault detected
7RESERVEDR0h Reserved
6PH_DIAG_ACTIVER0h PH_DIAG is active (one or more of PH_DIAG_xx is high)
  • 0h = PH_DIAG not currently active
  • 1h = PH_DIAG is currently active
5VDS_HAR0h VDS Overcurrent Status on the A High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
4VDS_LAR0h VDS Overcurrent Status on the A Low-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
3VDS_HBR0h VDS Overcurrent Status on the B High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
2VDS_LBR0h VDS Overcurrent Status on the B Low-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
1VDS_HCR0h VDS Overcurrent Status on the C High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
0VDS_LCR0h VDS Overcurrent Status on the C Low-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected

6.7.1.3 IC_STAT3 Register (Offset = 2h) [Reset = 0000h]

IC_STAT3 is shown in Table 6-14.

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Table 6-14 IC_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
15SHT_VDD_FLT_AR0h Short-to-battery status on phase A
  • 0h = No fault detected
  • 1h = Fault detected
14SHT_VDD_FLT_BR0h Short-to-battery status on phase B
  • 0h = No fault detected
  • 1h = Fault detected
13SHT_VDD_FLT_CR0h Short-to-battery status on phase C
  • 0h = No fault detected
  • 1h = Fault detected
12SHT_GND_FLT_AR0h Short-to-GND status on phase A
  • 0h = No fault detected
  • 1h = Fault detected
11SHT_GND_FLT_BR0h Short-to-GND status on phase B
  • 0h = No fault detected
  • 1h = Fault detected
10SHT_GND_FLT_CR0h Short-to-GND status on phase C
  • 0h = No fault detected
  • 1h = Fault detected
9OPEN_FLT_AR0h Open load status on phase A
  • 0h = No fault detected
  • 1h = Fault detected
8OPEN_FLT_BR0h Open load status on phase B
  • 0h = No fault detected
  • 1h = Fault detected
7OPEN_FLT_CR0h Open load status on phase C
  • 0h = No fault detected
  • 1h = Fault detected
6RESERVEDR0h Reserved
5VGS_HAR0h Gate driver fault status on the A High-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected
4VGS_LAR0h Gate driver fault status on the A Low-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected
3VGS_HBR0h Gate driver fault status on the B High-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected
2VGS_LBR0h Gate driver fault status on the B Low-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected
1VGS_HCR0h Gate driver fault status on the C High-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected
0VGS_LCR0h Gate driver fault status on the C Low-side MOSFET.
  • 0h = No fault detected
  • 1h = Fault detected

6.7.1.4 IC_STAT4 Register (Offset = 3h) [Reset = 0000h]

IC_STAT4 is shown in Table 6-15.

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Table 6-15 IC_STAT4 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h RESERVED
14DVDD_OVR0h DVDD overvoltage detection
  • 0h = No event is detected
  • 1h = DVDD overvoltage event detected
13VDRAIN_OVR0h VDRAIN overvoltage status
  • 0h = No fault detected
  • 1h = Fault detected
12VDRAIN_UVHR0h VDRAIN undervoltage status, High threshold
  • 0h = No fault detected
  • 1h = Fault detected
11VDRAIN_UVLR0h VDRAIN undervoltage status, Low threshold
  • 0h = No fault detected
  • 1h = Fault detected
10VCP_UVR0h VCP undervoltage status
  • 0h = No fault detected
  • 1h = Fault detected
9GVDD_OVR0h GVDD overvoltage status
  • 0h = No fault detected
  • 1h = Fault detected
8GVDD_UVHR0h GVDD undervoltage status, high threshold
  • 0h = No fault detected
  • 1h = Fault detected
7GVDD_UV_BSTR0h GVDD undervoltage status, BST
  • 0h = No fault detected
  • 1h = Fault detected
6RESERVEDR0h
5RESERVEDR0h
4VREF_UVR0h VREF undervoltage status
  • 0h = No fault detected
  • 1h = Fault detected
3BST_TIMEOUT_FLTR0h BST timeout fault during power-up (either BST_UV or VCP_UV remained high for longer than ~10ms during power-up sequence)
  • 0h = No fault detected
  • 1h = Fault detected
2BSTA_UVR0h BST undervoltage on the A High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
1BSTB_UVR0h BST undervoltage on the B High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected
0BSTC_UVR0h BST undervoltage on the C High-side MOSFET
  • 0h = No fault detected
  • 1h = Fault detected

6.7.1.5 IC_STAT5 Register (Offset = 4h) [Reset = 0000h]

IC_STAT5 is shown in Table 6-16.

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Table 6-16 IC_STAT5 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h RESERVED
14RESERVEDR0h RESERVED
13RESERVEDR0h
12RESERVEDR0h
11OTSD_TCPR0h Overtemperature Shutdown TCP Status Bit
  • 0h = No event is detected
  • 1h = Overtemperature shutdown TCP event detected
10OTSDR0h Overtemperature Shutdown Status Bit
  • 0h = No event is detected
  • 1h = Overtemperature shutdown event detected
9WDT_FLTR0h Watchdog timer fault status
  • 0h = No fault detected
  • 1h = Fault detected
8SPI_PAR_FLTR0h SPI parity bit fault status
  • 0h = No fault detected
  • 1h = Fault detected
7SPI_CRC_FLTR0h SPI CRC fault status
  • 0h = No fault detected
  • 1h = Fault detected
6SPI_ADDR_FLTR0h SPI address fault status
  • 0h = No fault detected
  • 1h = Attemped access to invalid register address detected
5SPI_CLK_FLTR0h SPI clock fault status
  • 0h = No fault detected
  • 1h = Incorrect number of SCLK cycles detected
4OTP_CRC_FLTR0h OTP CRC fault status
  • 0h = No fault detected
  • 1h = Fault in device OTP settings detected. Issuing a CLR_FLT command will enable gate drive output, but this fault reporting bit will remain latched.
3DEV_MODE_FLTR0h Device mode fault status
  • 0h = No fault detected
  • 1h = Fault detected
2RESERVEDR0h
1STP_FLTR0h Shoot-through protection fault status
  • 0h = No fault detected
  • 1h = Shoot-through input condition detected (INHx/INLx high simultaneously)
0DEADT_FLTR0h Deadtime protection fault status
  • 0h = No fault detected
  • 1h = Minimum dead time violation detected

6.7.1.6 IC_STAT6 Register (Offset = 5h) [Reset = 0000h]

IC_STAT6 is shown in Table 6-17.

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Table 6-17 IC_STAT6 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h
14RESERVEDR0h
13RESERVEDR0h
12RESERVEDR0h
11RESERVEDR0h
10RESERVEDR0h
9RESERVEDR0h
8RESERVEDR0h
7VDRAIN_UVOV_RAWR0h Un-latched status bit of VDRAIN OV/UV monitor output
  • 0h = No fault detected
  • 1h = Fault detected
6GVDD_UVOV_RAWR0h Un-latched status bit of GVDD OV/UV monitor output
  • 0h = No fault detected
  • 1h = Fault detected
5BST_VCP_UV_RAWR0h Un-latched status bit of BST UV and VCP UV monitor output
  • 0h = No fault detected
  • 1h = Fault detected
4VREF_UV_RAWR0h Un-latched status but of VREF UV monitor output
  • 0h = No fault detected
  • 1h = Fault detected
3DVDD_OV_RAWR0h Un-latched status bit of DVDD OV monitor output
  • 0h = No fault detected
  • 1h = Fault detected
2OTSD_RAWR0h Un-latched status bit of OTSD monitor output
  • 0h = No fault detected
  • 1h = Fault detected
1RESERVEDR0h
0RESERVEDR0h