SLVSHQ3 December   2025 DRV8363

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions 48-Pin DRV8363
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information 1pkg
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 SPI Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Three BLDC Gate Drivers
        1. 6.3.1.1 PWM Control Modes
          1. 6.3.1.1.1 6x PWM Mode
          2. 6.3.1.1.2 3x PWM Mode with INLx enable control
          3. 6.3.1.1.3 1x PWM Mode
        2. 6.3.1.2 Gate Drive Architecture
          1. 6.3.1.2.1 Bootstrap diode
          2. 6.3.1.2.2 VCP Trickle Charge pump
          3. 6.3.1.2.3 Gate Driver Output
          4. 6.3.1.2.4 Passive and Semi-active pull-down resistor
          5. 6.3.1.2.5 TDRIVE/IDRIVE Gate Drive Timing Control
          6. 6.3.1.2.6 Propagation Delay
          7. 6.3.1.2.7 Deadtime and Cross-Conduction Prevention
      2. 6.3.2 DVDD Linear Voltage Regulator
      3. 6.3.3 Low-Side Current Sense Amplifiers
        1. 6.3.3.1 Unidirectional Current Sense Operation
        2. 6.3.3.2 Bidirectional Current Sense Operation
      4. 6.3.4 Gate Driver Shutdown
        1. 6.3.4.1 DRVOFF Gate Driver Shutdown
        2. 6.3.4.2 Soft Shutdown Timing Sequence
      5. 6.3.5 Active Short Circuit
      6. 6.3.6 Gate Driver Protective Circuits
        1. 6.3.6.1  GVDD Undervoltage Lockout (GVDD_UV)
        2. 6.3.6.2  GVDD Overvoltage Fault (GVDD_OV)
        3. 6.3.6.3  VDRAIN Undervoltage Fault (VDRAIN_UV)
        4. 6.3.6.4  VDRAIN Overvoltage Fault (VDRAIN_OV)
        5. 6.3.6.5  VCP Undervoltage Fault (CP_OV)
        6. 6.3.6.6  BST Undervoltage Lockout (BST_UV)
        7. 6.3.6.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.6.8  MOSFET VGS Monitoring Protection
        9. 6.3.6.9  Shunt Overcurrent Protection (SNS_OCP)
        10. 6.3.6.10 Thermal Shutdown (OTSD)
        11. 6.3.6.11 Thermal Warning (OTW)
        12. 6.3.6.12 OTP CRC
        13. 6.3.6.13 SPI Watchdog Timer
        14. 6.3.6.14 Phase Diagnostic
    4. 6.4 Fault Detection and Response Summary Table (Fault Table)
    5. 6.5 Device Functional Modes
      1. 6.5.1 Gate Driver Functional Modes
        1. 6.5.1.1 Sleep Mode
        2. 6.5.1.2 Standby Mode
        3. 6.5.1.3 Active Mode
    6. 6.6 Programming
      1. 6.6.1 SPI
      2. 6.6.2 SPI Format
      3. 6.6.3 SPI Format Diagrams
    7. 6.7 Register Maps
      1. 6.7.1 STATUS Registers
      2. 6.7.2 CONTROL Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application with 48-pin package
        1. 7.2.1.1 External Components
      2. 7.2.2 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information

7.3.1 Layout Guidelines

  • Minimize length and impedance of GHx, SHx, GLx, and SLx traces. Use as few vias as possible to minimize parasitic inductance. TI also recommends to increase these trace widths to 15-20mil shortly after routing away from the device pin to minimize parasitic resistance.
  • Keep BSTx capacitors close to the respective pins. TI highly recommends to place this capacitor on the same side of the PCB to avoid parasitic via inductance.
  • Keep CPTH/CPTL flying capacitor as close to the device pins as possible. TI highly recommends to place this capacitor on the same side of the PCB to avoid parasitic via inductance.
  • Keep GVDD capacitor close to GVDD pin. TI highly recommends to place this capacitor on the same side of the PCB to avoid parasitic via inductance.
  • Keep DVDD capacitor close to DVDD pin. TI highly recommends to place this capacitor on the same side of the PCB to avoid parasitic via inductance. Additionally, the GND-return connection of the DVDD capacitor is routed directly back to the adjacent GND pin to avoid adding parasitic inductance and resistance to the DVDD regulator loop.
  • VDRAIN connection is routed such that the connection observes an "average" of the three phases to help maintain VDS accuracy. TI also recommends to connect VDRAIN close to the high-side bulk capacitance to help stabilize the input to VDRAIN and avoid exceeding the pin abs max rating. Keep VDRAIN capacitor close to VDRAIN pin to supply steady switching current for the charge pump.
  • Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance is placed such that the bulk capacitance minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces are as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and let the bulk capacitor deliver high current.
  • Connect SLx pins to individual MOSFET sources, not directly to GND, for accurate VDS detection and better transient resistance.
  • Route SNx/SPx pins in parallel from the sense resistor to the device. Place filtering components close to the device pins to minimize post-filter noise coupling. Verify that SNx/SPx stay separated from GND plane to achieve best CSA accuracy.
  • Place SO filtering components close to the MCU/ADC input to minimize post-filter noise coupling.
  • The exposed pad is used for thermal dissipation, not electrical grounding, and has a high-impedance connection to the GND/AGND pins. Therefore, TI recommends to connect the exposed pad to the best thermal GND, and to connect the GND/AGND pins to the MCU-reference GND.