SLVSI15A March   2025  – December 2025 TPSM8287B15 , TPSM8287B30

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Output Voltage Setting
        1. 7.3.5.1 Output Voltage Setpoint
        2. 7.3.5.2 Output Voltage Range
        3. 7.3.5.3 Non-Default Output Voltage Setpoint
        4. 7.3.5.4 Dynamic Voltage Scaling (DVS)
        5. 7.3.5.5 Droop Compensation
      6. 7.3.6  Compensation (COMP)
      7. 7.3.7  Mode Selection / Clock Synchronization (MODE/SYNC)
      8. 7.3.8  Spread Spectrum Clocking (SSC)
      9. 7.3.9  Output Discharge
      10. 7.3.10 Undervoltage Lockout (UVLO)
      11. 7.3.11 Overvoltage Lockout (OVLO)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 Cycle-by-Cycle Current Limiting
        2. 7.3.12.2 Hiccup Mode
        3. 7.3.12.3 Current-Limit Mode
      13. 7.3.13 Power Good (PG)
        1. 7.3.13.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.13.2 Power-Good Secondary Device Behavior
      14. 7.3.14 Remote Sense
      15. 7.3.15 Thermal Warning and Shutdown
      16. 7.3.16 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Two TPSM8287B30x in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.16 Stacked Operation

The user can connect multiple devices in parallel in what is known as a "stack" to increase output current capability, to reduce device junction temperature or the output voltage ripple. For example, paralleling four 30A devices can provide up to 120A of current. More devices can be stacked, as long as the PCB layout maintains the integrity of the shared signals between the modules.

A stack comprises one primary device and one or more secondary devices. During initialization, each device monitors the SYNC_OUT pin to determine if the device must operate as a primary device or a secondary device:

  • If there is a 47kΩ resistor between the SYNC_OUT pin and ground, the device operates as a secondary device.
  • If the SYNC_OUT pin is high impedance, the device operates as a primary device.

The following figure shows the recommended interconnections in a stack of two TPSM8287Bxx devices.


TPSM8287B15 TPSM8287B30 Two TPSM8287Bxx Devices in a Stacked Configuration

Figure 7-17 Two TPSM8287Bxx Devices in a Stacked Configuration

The key points to note are:

  • All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at least 15kΩ.
  • All secondary devices must connect a 47kΩ resistor between the SYNC_OUT pin and ground.
  • All the devices in the stack share a common power-good signal, which must be pulled up with a resistor to a logic high level.
  • All the devices in the stack share a common compensation signal.
  • In case many devices are stacked, the parasitic capacitance of the COMP trace can affect the loop performance. To decouple this trace capacitance from the primary device and the compensation network, a unity gain buffer can be used between the primary and all secondary devices.
  • VOSNS and GOSNS of the primary device must be connected to the capacitor at the load
  • VOSNS and GOSNS of the secondary devices can either be connected to the output capacitor at the device or alternatively both pins can be tied to AGND. Do not leave these pins floating.
  • The same device part number (with the same output current) must be used for all devices in the stack.
  • The primary device must be configured for forced PWM operation (secondary devices are automatically configured for forced PWM operation).
  • A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
  • Only the VSETx pins of the primary device are used to set the default output voltage. The VSETx pins of secondary devices are not used and must be connected to ground.
  • The SDA and SCL pins of secondary devices are not used and must be connected to ground.
  • A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase offset relative to the previous device in the daisy-chain. This phase offset can configured to approximately 180° (default) or 120° through the SYNC_OUT_PHASE bit in the CONTROL2 register. To daisy-chain the clocking signal, connect the SYNC_OUT pin of the primary device to the MODE/SYNC pin of the first secondary device. Connect the SYNC_OUT pin of the first secondary device to the MODE/SYNC pin of the second secondary device. Continue this connection scheme for all devices in the stack to daisy-chain them together.
  • Hiccup overcurrent protection must not be used in a stacked configuration.
  • For output voltages >=1.2V, reduce the maximum output current per phase by 1A to account for current balancing inaccuracy.

In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see Section 7.3.3). Each device in the stack can pull the EN pin low during device start-up or when a fault occurs. Thus, the stack is only enabled when all devices have completed the start-up sequence and are fault-free. A fault in any one device disables the whole stack for as long as the fault condition exists.

During start-up, the primary converter pulls the COMP pin low for as long as the enable signal (SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP pin and all converters in the stack follow the COMP voltage. During start-up, each device in the stack pulls the PG pin low while the device initializes. When initialization is complete, each secondary device in the stack sets the PG pin to high impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when the stack has completed the start-up ramp and the output voltage is within the power-good window. The secondary converters in the stack detect the rising edge of the power-good signal and switch to FPWM operation. After the stack has successfully started up, the primary device controls the power-good signal in the normal way.

Functionality During Stacked Operation

Some device features are not available during stacked operation, or are only available in the primary converter. Table 7-6 summarizes the available functionality during stacked operation.

Table 7-6 Functionality During Stacked Operation
FUNCTION PRIMARY DEVICE SECONDARY DEVICE REMARK
UVLO Yes Yes Common enable signal
OVLO Yes Yes Common enable signal
OCP – current limit Yes Yes Individual device
OCP – hiccup OCP No No Do not use during stacked operation
Thermal shutdown Yes Yes Common enable signal
Power Good (window comparator) Yes No Primary device only
I2C interface Yes No Primary device only
DVS Through I2C No Voltage loop controlled by primary device only
SSC Through I2C Yes, through primary device Daisy-chained from primary device to secondary devices
SYNC Yes Yes, through primary device Synchronization clock applied to primary device and daisy-chained from primary device to secondary devices
Precise enable No No Only binary enable
Output discharge Through I2C Yes Always enabled in secondary devices

Fault Handling During Stacked Operation

In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal. Table 7-7 summarizes the fault handling during stacked operation.

Table 7-7 Fault Handling During Stacked Operation
FAULT CONDITIONDEVICE RESPONSESYSTEM RESPONSE
UVLOEnable signal pulled lowNew soft start
OVLO
Thermal shutdown
Current limitEnable signal remains highError amplifier clamped
External CLK applied to MODE/SYNC failsSYNC_OUT and power-stage switch to internal oscillatorNormal operation at the default switching frequency. Secondary devices remain properly phase-shifted.