SLVSI15A March   2025  – December 2025 TPSM8287B15 , TPSM8287B30

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Output Voltage Setting
        1. 7.3.5.1 Output Voltage Setpoint
        2. 7.3.5.2 Output Voltage Range
        3. 7.3.5.3 Non-Default Output Voltage Setpoint
        4. 7.3.5.4 Dynamic Voltage Scaling (DVS)
        5. 7.3.5.5 Droop Compensation
      6. 7.3.6  Compensation (COMP)
      7. 7.3.7  Mode Selection / Clock Synchronization (MODE/SYNC)
      8. 7.3.8  Spread Spectrum Clocking (SSC)
      9. 7.3.9  Output Discharge
      10. 7.3.10 Undervoltage Lockout (UVLO)
      11. 7.3.11 Overvoltage Lockout (OVLO)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 Cycle-by-Cycle Current Limiting
        2. 7.3.12.2 Hiccup Mode
        3. 7.3.12.3 Current-Limit Mode
      13. 7.3.13 Power Good (PG)
        1. 7.3.13.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.13.2 Power-Good Secondary Device Behavior
      14. 7.3.14 Remote Sense
      15. 7.3.15 Thermal Warning and Shutdown
      16. 7.3.16 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Two TPSM8287B30x in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.5.1 Output Voltage Setpoint

During initialization, the device reads the state of the VSETx pins and selects the default output voltage according to Table 7-2. Note that the VSETx pins also select the I2C target address of the device and the setting of the VRANGE bits located in register CONTROL2. The VSETx pins are only read during a power cycle of VIN or by setting RESET = 1 through the I2C interface. Changing the configuration after VIN is present does not affect the content of the registers or the I2C address. Make sure that there is no stray current path connected to the VSETx pins and that the parasitic capacitance between the VSETx pins and GND is less than 100pF. For proper operation, the input voltage needs to be at least 1.5V above the selected output voltage.

Table 7-2 Start-Up Output Voltage and I2C Address
VSET1VSET2I2C ADDRESSTPSM8287BxxL VOUT VOLTAGE(1)TPSM8287BxxH VOUT VOLTAGE(2)
GNDGND0x45400mV800mV
GND47kΩ to GND0x44425mV850mV
GND47kΩ to VIN0x47450mV900mV
GNDVIN0x46475mV950mV
47kΩ to GNDGND0x45500mV1000mV
47kΩ to GND47kΩ to GND0x44525mV1050mV
47kΩ to GND47kΩ to VIN0x47550mV1100mV
47kΩ to GNDVIN0x46575mV1150mV
47kΩ to VINGND0x45600mV1200mV
47kΩ to VIN47kΩ to GND0x44625mV1250mV
47kΩ to VIN47kΩ to VIN0x47650mV1300mV
47kΩ to VINVIN0x46675mV1350mV
VINGND0x45700mV1400mV
VIN47kΩ to GND0x44725mV1450mV
VIN47kΩ to VIN0x47750mV1500mV
VINVIN0x46775mV1550mV
(1) The device sets VRANGE = 01b.
(2) The device sets VRANGE = 10b.

If the user programs new output voltage setpoints (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time (SSTIME[1:0]) settings when the device has already begun the soft-start sequence, the device ignores the new values until the soft-start sequence is complete. The output voltage ramps up to the target value set by the VSETx pins, before ramping up or down to any new value programmed to the device over the I2C interface. When changing VOUT[7:0], VRAMP[1:0], or SSTIME[1:0] while EN is low, the device uses the new values the next time the device is enabled.