SLVSI15 Data sheet

SLVSI15B March 2025 – October 2026 TPSM8287B15 , TPSM8287B30

PRODMIX

9.2.2.4 Selecting the Output Capacitors

In practice, the total output capacitance is typically comprised of a combination of different capacitors, in which larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher frequencies to satisfy the load impedance requirements. The value, type, and location of the output capacitors are typically defined by the load. TI recommends X7R multilayer ceramic capacitors (MLCCs) for best filtering and must be placed between both VOUT and PGND pins, as close as possible to those pins. For applications with ambient temperatures below 85°C, capacitors with an X5R dielectric can be used. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Select the right capacitors carefully in combination with considering the package size and voltage rating. The below calculations use the effective value of the total output capacitance.

The TPSM8287Bxx devices feature a butterfly or parallel layout with VOUT and PGND pins on opposite sides of the package. This feature allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields cancel each other out, thereby reducing EMI. Additionally, some device variants of the TPSM8287Bxx integrate two high frequency and two bulk output capacitors to further reduce the area of the output loops and reduce the required external capacitance. Those two integrated bulk capacitors can be considered to have a minimum effective capacitance of 7µF each. For details on which device versions have integrated output capacitors, please refer toSection 4.

The TPSM8287Bxx device is optimized to support harsh load transients. The device external loop compensation tunes the loop response to the desired response with a given output capacitance. The below calculations create designs that meet the load step specified in Table 9-2. These calculations typically result in total output capacitances of several hundred µF.

Best output voltage regulation is achieved when the TPSM8287Bxx device, the output capacitors, and load are placed very close to each other, keeping the distance and added inductance between the device and load to the absolute minimum.

In case this placement cannot be achieved, then most of the total capacitance must be located at the load, with just two capacitors located at the TPSM8287Bxx device. TI recommends that the capacitance located at the load to be at least equal to the amount of the capacitance located at the device.

If the application does not contain harsh load transients, then smaller values of output capacitances are possible. Do not use output capacitances below the minimum values in Recommended Operating Conditions.

The transient response of the converter is defined by one of two criteria:

The slew rate of the current through the inductor, in which case the feedback loop of the converter saturates.
The loop bandwidth, in which the converter stays in regulation, and the loop does not saturate (BW_τ < f_SW / 4)

Which of the above criteria applies in any given application depends on the operating conditions and component values used. Calculate the output capacitance for both cases and select the higher of the two values.

If the converter remains in regulation, the minimum required output capacitance is given by:

Equation 17.

C_{O U T (m i n) (r e g)} = (\frac{τ \times g_{m} \times R_{Comp 1}}{2 \times π \times \frac{L}{Nɸ} \times {BW}_{τ}}) (1 + \sqrt{{T O L}_{I N D}^{2} + {T O L}_{f S W}^{2}})

Equation 18.

C_{O U T (m i n) (r e g)} = (\frac{12.5 \times 10^{- 6} \times 1.5 \times 10^{- 3} \times 301}{2 \times π \times \frac{50 \times 10^{- 9}}{1} \times 200 \times 10^{3}}) (1 + \sqrt{{20 %}^{2} + {10 %}^{2}}) = 110 μ F

If the converter loop saturates, the minimum output capacitance is given by:

Equation 19.

C_{O U T (m i n) (s a t)} = \frac{1}{∆ V_{O U T}} (\frac{L \times {∆ I_{OUT(max)}}^{2}}{2 \times V_{O U T} \times Nɸ} - \frac{∆ I_{OUT(step)} \times t_{t}}{2}) (1 + {T O L}_{I N D})

Equation 20.

C_{O U T (m i n) (s a t)} = \frac{1}{25 \times 10^{- 3}} (\frac{50 \times 10^{- 9} \times 6 . 6^{2}}{2 \times 0.6 \times 1} - \frac{3.0 \times 1 \times 10^{- 6}}{2}) (1 + 20 %) = 15 μ F

In this case, choose C_{OUT(min)(reg)} = 110µF as the larger of the two values for the output capacitance.

Table 9-3 lists the output capacitors chosen. 2 × 22µF capacitors are placed close to the IC, giving a minimum effective capacitance of about 15µF each. A combination of 2 × 10µF, 2 × 22µF and 1 × 47µF capacitors are placed near the load to provide a low impedance for load transients and low output voltage ripple. These capacitors yield about 99µF of effective capacitance. Device variants with capacitors integrated inside the module provide an additional 14µF. Together, the 113µF of effective capacitance is very close to the required minimum value calculated above. For further calculations, use C_{OUT_eff} = 113µF.

Equation 46 checks that most of the output capacitance is placed at the load. If the ratio is less than 1, increase the capacitance at the load or place the device, output capacitance, and load next to each other such that there is no separation between the output capacitances.

Equation 21.

\frac{C_{LOAD_eff}}{C_{Converter_eff} + C_{Integrated_eff}} > 1

Equation 22.

\frac{69 \times 10^{- 6}}{2 \times 15 \times 10^{- 6} + 14 \times 10^{- 6}} > 1

= True

Equation 23 calculates the output voltage ripple, based on the effective output capacitance value.

Equation 23.

V_{O U T (p - p)} = \frac{I_{L (PP)}}{8 \times C_{OUT_eff} \times f_{s w}}

Equation 24.

V_{O U T (p - p)} = \frac{7.2}{8 \times 113 \times 10^{- 6} \times 1.5 \times 10^{6}} = 5.3 m V

The ripple can be slightly higher in the application, due to the ESR and ESL in the output capacitors and the application board parasitics.