4 Pin Configuration and Functions

TPS546B25 RXX 37-Pin WQFN-FCRLF Package (Top View)

Figure 4-1 RXX 37-Pin WQFN-FCRLF Package
(Top View)

TPS546B25 RXX 37-Pin WQFN-FCRLF Package (Bottom View)

Figure 4-2 RXX 37-Pin WQFN-FCRLF Package (Bottom View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
AGND	32	G	Analog ground pin, reference point for internal control circuitry
BOOT	26	P	Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. TI recommends a 10V, X7R or better, 0.1μF or greater value ceramic capacitor. The capacitor must have at least 50nF of capacitance after DC bias derating at 5V.
CNTL	27	I	CTRL pin, an active-high input pin that, when asserted high, causes the converter to begin the soft-start sequence for the output voltage rail.
GOSNS	31	I	Negative input of the differential remote sense circuit, connect to the ground sense point on the load side.
ISHARE	1	I/O	ISHARE pin for stackable configuration. Tie this pin to other ISHARE pins in the stack. Do not connect (float) in standalone configuration.
MSEL1	36	I	Use a resistor to AGND to select primary, secondary device, internal, external feedback, current limit, and fault response options. See Pin-Strapping.
MSEL2	6	I	Use a resistor to AGND to select switching frequency, ramp, and gain compensation options for the device. See Pin-Strapping.
NC	37		Not connected. This pin is floating internally.
PG	2	O	Open-drain power-good indicator
PGND	7, 8, 9, 10, 19	G	Power ground for the internal power stage
PHASE	25	I/O	Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap capacitor from BOOT pin to PHASE pin.
PMB_ADDR/VORST#	29	I	Use a resistor to AGND to select the PMBus address light load operating mode, DCM or FCCM, and multiphase stacking options. See Pin-Strapping.
PMB_CLK	34	I	PMBus clock pin, open drain
PMB_DATA	33	I/O	PMBus bi-directional data pin, open drain
PVIN	20, 21, 22, 23, 24	P	Power input for both the power stage and the input of the internal VCC LDO
SMB_ALERT_#	35	O	SMBALERT# as described in the SMBus specification. The pin is open-drain. The SMBALERT# indicator is used in conjunction with the Alert Response Address (ARA). During nominal operation, the SMBALERT# is held high.
SW	11 – 18	O	Output switching terminal of the power converter. Connect these pins to the output inductor.
TRIGGER	3	I/O	TRIGGER pin for stackable configuration. Tie this pin to other TRIGGER pins in the stack. Do not connect (float) in standalone configuration.
VCC	4	P	Output of internal 4.5V LDO from PVIN and Supply for analog control circuitry. Bypass with a 10V rated X5R or better 2.2μF capacitor to AGND and connect to VDRV with a 1Ω resistor. Check layout guidelines for more details.
VDRV	5	—	5V supply for gate drivers. Bypass to PGND with a 10V rated X5R or better 2.2μF and connect to VCC with a 1Ω resistor. An external 5V bias can be connected to this pin to reduce power losses on the internal LDO or to allow operation with a lower PVIN voltage. Check layout guidelines for more details.
VOSNS	30	I	Output voltage sense pin and positive input of the differential remote sense circuit. For both internal and external feedback, connect VOSNS to the Vout sense point with no more than 100Ω of resistance.
VSEL/FB	28	I	When the device is configured to use the internal FB divider, this pin is VSEL. Use a resistor to AGND to select the output voltage. See Programming MSEL1 and Programming VSEL\FB. When the device is configured for an external resister divider, this pin is the feedback pin of the device. Connect this pin to VOSNS and GOSNS with a resistor divider to set the output voltage. See Layout Guidelines

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.