SLVSI89A March   2026  – June 2026 TPS63820

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Scheme
        1. 7.3.1.1 Buck Operation
        2. 7.3.1.2 Boost Operation
        3. 7.3.1.3 Buck-Boost Operation
      2. 7.3.2  PFM Operation
      3. 7.3.3  Ultra-sonic Mode Operation
      4. 7.3.4  Forced-PWM Operation (FPWM)
      5. 7.3.5  Ramp-PWM Operation (RPWM)
      6. 7.3.6  Device Enable (EN)
      7. 7.3.7  Undervoltage Lockout (UVLO)
      8. 7.3.8  Soft Start
      9. 7.3.9  Dynamic Voltage Scaling
      10. 7.3.10 Protection Functions
        1. 7.3.10.1 Input Voltage Protection (IVP)
        2. 7.3.10.2 Output Voltage Protection (OVP)
        3. 7.3.10.3 Current Limit Mode and Overcurrent Protection
        4. 7.3.10.4 Output Short-Circuit Protection (Hiccup)
        5. 7.3.10.5 Thermal Shutdown
      11. 7.3.11 Power Good
      12. 7.3.12 Load Disconnect
      13. 7.3.13 Output Discharge
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
  9. 8 Register Map
    1. 8.1 Register Description
      1. 8.1.1 Register Map
      2. 8.1.2 Register CONTROL (Register address: 0x01; Default: 0xE0 or 0x40)
      3. 8.1.3 Register STATUS (Register address: 0x02; Default: 0x00)
      4. 8.1.4 Register DEVID (Register address: 0x03; Default: 0x20)
      5. 8.1.5 Register VOUT1 (Register address: 0x04; Default: 0x54)
      6. 8.1.6 Register CONTROL2 (Register address: 0x06; Default: 0x08)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 1.2V to 5.5V Output Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection
          2. 9.2.1.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     79

7.3.4 Forced-PWM Operation (FPWM)

During forced-PWM operation, the device uses PWM for all operating conditions. Forced-PWM operation has lower output voltage ripple and better transient response than power-save mode operation, but lower efficiency at low output currents (see Table 7-1).

Note that the device inhibits forced-PWM operation during start-up (that is, until the converter output has reached power-good for the first time).

To enable forced-PWM operation, set the FPWM bit in the Control register to 1.