The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 2.2µF of ceramic capacitance is required on the input of the LM5168E regulator, connected directly between VIN and GND. This must be rated for at least the maximum input voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. More input capacitance is required for larger output currents. Keep in mind that the value of 2.2µF is the actual value after all derating is applied. For this example, four 1µF, 250V, X7R (or better) ceramic capacitors are chosen due to voltage derating. If larger case size, higher voltage capacitors, or both can be used, then the total number can be reduced. Designs with reduced input voltage range can use capacitors with lower voltage ratings.

Many times, using an electrolytic capacitor on the input in parallel with the ceramics is desirable. This statement is especially true if long leads or traces (greater than about 5cm) are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. Use Equation 25 to calculate the approximate RMS current. This value must be checked against the manufacturers' maximum ratings.

The input capacitor is part of the buck converter high di/dt current loop. The high di/dt current, together with excessive parasitic inductance between the IC and the input capacitor, can result in excessive voltage ringing on the SW node of the IC. The placement of the input capacitor on the board is critical for minimizing the parasitic inductance in the high di/dt loop and accordingly minimizing the SW node ringing at each switching transition.

For designs targeting the maximum operating voltage of the regulator, make sure the ringing on the SW node does not exceed the absolute maximum rating of the device. The SW node ringing is a function of how well the input capacitor is positioned with respect to the IC. Refer to the PCB layout example in Figure 8-28 for proper placement of the input capacitors.