SLVSIY7 August   2025 LM5168E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Architecture
      2. 7.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 7.3.3  Internal Soft Start
      4. 7.3.4  On-Time Generator
      5. 7.3.5  Current Limit
      6. 7.3.6  N-Channel Buck Switch and Driver
      7. 7.3.7  Synchronous Rectifier
      8. 7.3.8  Enable/Undervoltage Lockout (EN/UVLO)
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Sleep Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Buck Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency (RT)
        2. 8.2.2.2 Buck Inductor Selection
        3. 8.2.2.3 Setting the Output Voltage
        4. 8.2.2.4 Type 3 Ripple Network
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Considerations
        7. 8.2.2.7 CBST Selection
        8. 8.2.2.8 Example Design Summary
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact PCB Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Thermal Considerations
      3. 8.4.3 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Guidelines

PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply performance.

  • Bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with a high-quality dielectric to help eliminate these problems. Place CIN as close as possible to the LM5168E VIN and GND pins. Grounding for both the input and output capacitors must consist of localized top-side planes that connect to the GND pin and GND PAD.
  • Minimize the loop area formed by the input capacitor connections to the VIN and GND pins. The input capacitor is part of the buck converter high di/dt current loop. The high di/dt current, together with excessive parasitic inductance between the IC and the input capacitor, can result in excessive voltage ringing on the SW node of the IC. The placement of the input capacitor on the board is critical for minimizing the parasitic inductance in the high di/dt loop and accordingly minimizing the SW node ringing at each switching. For designs targeting the maximum operating voltage of the regulator, make sure the ringing on the SW node does not exceed the absolute maximum rating of the device. The SW node voltage ringing is a function of how well the input capacitor is positioned with respect to the IC. Refer to the PCB layout example in Figure 8-28 for proper placement of the input capacitors.
  • Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive capacitive coupling.
  • Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
  • Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
  • Have a single-point ground connection to the plane. Route the ground connections for the feedback, and enable components to the ground plane. This action prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior.
  • Make VIN, VOUT, and ground bus connections as wide as possible. This guidelines reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
  • Minimize the trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place CFF (if used) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on the other side of a grounded shielding layer.
  • Note that the RT pin is sensitive to noise. Therefore, locate the RT resistor as close as possible to the device and route with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20pF.
  • Provide adequate heat sinking for the LM5168E to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.