SLVSJJ4 October   2025 SN74LVC1G09B-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5.   5
  6. Pin Configuration and Functions
  7. Specifications
    1. 5.1 Specifications
      1. 5.1.1 Absolute Maximum Ratings
      2. 5.1.2 ESD Ratings
      3. 5.1.3 Recommended Operating Conditions
      4. 5.1.4 Thermal Information
      5. 5.1.5 Electrical Characteristics
      6. 5.1.6 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Open-Drain CMOS Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Open-Drain CMOS Outputs

This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the high logical state, open-drain outputs are in a high-impedance state. The drive capability of this device can create fast edges into light loads, so consider routing and load conditions to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Limit the device output power to avoid damage due to overcurrent. Follow the electrical and thermal limits defined in the Absolute Maximum Ratings at all times.

When placed into the high-impedance state, the output neither sources nor sinks current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor depends on multiple factors, including parasitic capacitance and power consumption limitations. Typically, use a 10kΩ resistor to meet these requirements.

Leave unused open-drain CMOS outputs disconnected.