SLVSJW9 May   2026 PCA9306H

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics (Translating Down)
    7. 5.7 Switching Characteristics (Translating Up)
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Definition of threshold voltage
      2. 7.1.2 Correct Device Set Up
      3. 7.1.3 Switch and Translation Configuration
      4. 7.1.4 Negative Glitch Immunity
      5. 7.1.5 Controller on Side 1 or Side 2 of Device
      6. 7.1.6 LDO and PCA9306H Concerns
      7. 7.1.7 Current Limiting Resistance on VREF2
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN) Pin
      2. 7.3.2 Voltage Translation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Applications of I2C
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bidirectional Voltage Translation
        2. 8.2.2.2 Sizing Pullup Resistors
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12.   Mechanical, Packaging, and Orderable Information

7.3.1 Enable (EN) Pin

The PCA9306H device is a double-pole, single-throw switch in which the gate of the transistors is controlled by the voltage on the EN pin. In Figure 8-1, the PCA9306H device is always enabled when power is applied to VREF2. In Figure 8-2, the device is enabled when a control signal from a processor is in a logic-high state.