SLVSKC2A October   2025  – December 2025 TPS7E81

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Shutdown
      5. 6.3.5 Foldback Current Limit
      6. 6.3.6 Power Limit
      7. 6.3.7 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistor Selection
      2. 7.1.2 Recommended Capacitor Types
      3. 7.1.3 Input and Output Capacitor Selection
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor
      6. 7.1.6 Dropout Voltage
      7. 7.1.7 Estimating Junction Temperature
      8. 7.1.8 Power Dissipation (PD)
      9. 7.1.9 Power Dissipation Versus Ambient Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Choose Feedback Resistors
      3. 7.2.3 Power Supply Recommendations
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Layout Guidelines

For best overall performance, follow the guidelines in this section. Place all circuit components on the same side of the printed circuit board (PCB) and as near as practical to the respective LDO pin connections. Place ground return connections for the input and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or resistor divider. This practice negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to provide accuracy of the output voltage and shield the LDO from noise. To improve the thermal performance of the device, and to maximize the current output at high ambient temperature, spread the copper under the thermal pad as far as possible and place enough thermal vias on the copper under the thermal pad. Figure 7-6 and Figure 7-7 show example layout for TPS7E81 packages.