The TDEL3G511 device contains three digitally timed rising-edge delay circuits.

When the input transitions from low to high, the internal timer starts. When the timer reaches the predefined delay value, the output transitions from low to high and the timer is disabled. When the input transitions from high to low, the timer is reset and disabled, awaiting the next rising-edge delay operation.

The rising-edge delay feature provides inherent filtering behavior for active-high signals, maintaining the output in the low state as long as the input does not remain high longer than the predefined delay time.

The internal oscillator turns off when not in use. When a delay is being measured, the oscillator is turned on and is shared by all channels.

During the power-up ramp, the outputs remain in a high-impedance state until the internal power-on reset circuit enables normal device operation.