SLVSKD3
April 2026
TDEL3G511
PRODUCTION DATA
1
1
Features
2
Applications
4
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Characteristics
5.7
Switching Characteristics
5.8
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Naming Convention
7.3.2
Timing Mechanism and Accuracy
7.3.3
CMOS Push-Pull Outputs
7.3.4
CMOS Schmitt-Trigger Inputs
7.3.5
Latching Logic with Known Power-Up State
7.3.6
Clamp Diode Structure
7.4
Device Functional Modes
7.4.1
Startup Operation
7.4.2
On-State Operation
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Device Nomenclature
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
1% typical, 10% maximum delay variation
Pre-configured digital timing - no external timing components required
Wide operating range from 1.65V to 5.5V
I/O clamp diodes protect from over- and under-voltage transients
Schmitt-trigger architecture on all inputs