SLVSKF8 October   2025 SN74ACT125-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Wettable Flanks
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM (INPUT) TO (OUTPUT) V#b#CC -40°C to 125°C UNIT
MIN TYP MAX
CL = 15pF
tPLH A Y 4.5 V 2.3 4.2 6.6 ns
tPHL 4.5 V 2.8 4.8 7.2
tPLZ OE Y 4.5 V 1.5 2.7 4.4 ns
tPHZ 4.5 V 2.3 4.2 6.6
tPZL OE Y 4.5 V 2.8 4.9 7.5 ns
tPZH 4.5 V 3.2 5.5 8.4
tr Y 4.5 V 0.6 1.3 2.2 ns
tf 4.5 V 0.6 1.2 1.8
tsk(o) Y 4.5 V 0 0.1 ns
tPLH A Y 5.5 V 2.2 3.9 6.1 ns
tPHL 5.5 V 2.5 4.2 6.2
tPLZ OE Y 5.5 V 1.5 2.7 4.2 ns
tPHZ 5.5 V 2.3 4 6.2
tPZL OE Y 5.5 V 2.5 4.2 6.4 ns
tPZH 5.5 V 2.9 4.8 7.1
tr Y 5.5 V 0.5 1.2 2 ns
tf 5.5 V 0.6 1.1 1.6
tsk(o) Y 5.5 V 0 0.2 ns
CL = 50pF
tPLH A Y 4.5 V 2.9 5.2 8.1 ns
tPHL 4.5 V 3.3 5.7 8.7
tPLZ OE Y 4.5 V 1.8 3.1 4.8 ns
tPHZ 4.5 V 2.9 5.2 8.1
tPZL OE Y 4.5 V 3.5 6 9.1 ns
tPZH 4.5 V 3.9 6.7 10.2
tr Y 4.5 V 1.2 2.7 4.5 ns
tf 4.5 V 1.2 2.3 3.6
tsk(o) Y 4.5 V 0.1 0.2 ns
tPLH A Y 5.5 V 2.8 4.9 7.6 ns
tPHL 5.5 V 3 5 7.4
tPLZ OE Y 5.5 V 1.7 3 4.6 ns
tPHZ 5.5 V 2.6 4.6 7
tPZL OE Y 5.5 V 3.1 5.3 7.9 ns
tPZH 5.5 V 3.5 5.8 8.8
tr Y 5.5 V 1.1 2.4 4 ns
tf 5.5 V 1.2 2.1 3.2
tsk(o) Y 5.5 V 0.1 0.2 ns
CL = 150pF
tPLH A Y 4.5 V 4 7.2 11.4 ns
tPHL 4.5 V 4.4 7.5 11.3
tPLZ OE Y 4.5 V 3.2 4.9 6.9 ns
tPHZ 4.5 V 5.4 8.2 11.5
tPZL OE Y 4.5 V 4.9 8.2 12.4 ns
tPZH 4.5 V 5.3 8.9 13.5
tr Y 4.5 V 2.8 6.3 10.8 ns
tf 4.5 V 2.7 4.9 7.7
tsk(o) Y 4.5 V 0.1 0.2 ns
tPLH A Y 5.5 V 3.7 6.7 10.6 ns
tPHL 5.5 V 3.9 6.5 9.8
tPLZ OE Y 5.5 V 2.9 4.5 6.3 ns
tPHZ 5.5 V 4.4 6.9 9.9
tPZL OE Y 5.5 V 4.3 7.2 10.8 ns
tPZH 5.5 V 4.8 8 12
tr Y 5.5 V 2.4 5.4 9.3 ns
tf 5.5 V 2.4 4.4 6.9
tsk(o) Y 5.5 V 0.1 0.3 ns
CPD(1) Any 5V 15 pF
(1) Power dissipation capacitance is calculated using the method described in CMOS Power Consumption and Cpd Calculation.