SLVSKU8 July   2026 TPS55285A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  Default Output Enable (OE) Bit Status
      3. 6.3.3  Input Undervoltage Lockout
      4. 6.3.4  Enable and Programmable UVLO
      5. 6.3.5  Soft Start
      6. 6.3.6  Shutdown and Load Discharge
      7. 6.3.7  Switching Frequency
      8. 6.3.8  Switching Frequency Dithering
      9. 6.3.9  Inductor Current Limit
      10. 6.3.10 Internal Charge Path
      11. 6.3.11 Output Voltage Setting
      12. 6.3.12 Output Current Limit
      13. 6.3.13 Output Cable Voltage Drop Compensation
      14. 6.3.14 Input Overvoltage Protection
      15. 6.3.15 Output Overvoltage Protection
      16. 6.3.16 Output Short-Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 Target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]
    2. 7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]
    3. 7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]
    4. 7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]
    5. 7.5 CDC Register (Address = 5h) [reset = 11110000b]
    6. 7.6 MODE Register (Address = 6h) [reset = 00100000b]
    7. 7.7 STATUS Register (Address = 7h) [reset = 00000001b]
    8. 7.8 Register Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6 MODE Register (Address = 6h) [reset = 00100000b]

MODE is shown in Figure 7-7 and described in Table 7-8.

Return to Summary Table.

MODE controls the operating mode of the TPS55285A.

DISCHG_2 bit controls the discharge FET enabled or disabled when Vout steps down. When DISCHG_2 is set to 1, the discharge FET current helps reducing the reverse current in FPWM mode when Vout steps down.

Figure 7-7 MODE Register
76543210
OESPREAD SPECTRUMHICCUPDISCHGFSWFPWMDISCHG_2
R/W-0bR/W-0bR/W-1bR/W-0bR/W-00bR/W-0bR/W-0b
Table 7-8 MODE Register Field Descriptions
BitFieldTypeResetDescription
7OER/W0bOutput enable

0b = Output disabled (Default)

1b = Output enable

6SPREADSPECTRUMR/W0bSpread spectrum function

0b = Disable spread spectrum function (Default)

1b = Enable spread spectrum function

5HICCUPR/W1bHiccup mode

0b = Disable the hiccup during output short circuit protection.

1b = Enable the hiccup during output short circuit protection (Default)

4DISCHGR/W0bOutput discharge

0b = Disabled VOUT discharge when the device is in shutdown mode (Default)

1b = Enable VOUT discharge. VOUT is discharged to ground by an internal 100mA current sink in shutdown mode

3-2FSWR/W00bSwitching frequency

00b = 400kHz (Default)

01b = 800kHz

11b = 1.6MHz

11b = 2.1MHz

1FPWMR/W0bSelect operating mode at light load condition

0b = PFM operating mode at light load condition (Default)

1b = FPWM operating mode at light load condition

0DISCHG_2R/W0b

0b = Output discharge function is enabled when VREF voltage decreases. (Default)

1b = Output discharge function is disabled when VREF voltage decreases.