SLVSLU1 June   2026 ADS9324C

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
      4. 7.4.4 Programming
        1. 7.4.4.1 Register Write Operation
        2. 7.4.4.2 Register Read Operation
        3. 7.4.4.3 Initialization Example - DOUT Lane Configuration
        4. 7.4.4.4 Initialization Example - Digital Filter
        5. 7.4.4.5 Initialization Example - Common Mode Error Correction
        6. 7.4.4.6 Initialization Example - ADC Calibration
        7. 7.4.4.7 Initialization Example - Test Pattern Mode
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 16S Battery Cell Voltage Monitoring
    2. 9.2 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
        1. 9.3.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 12.1 Tape and Reel Information

7.4.4.3 Initialization Example - DOUT Lane Configuration

By default, ADC output interface is configured in 8-lane mode with 16-bit ADC output size. Table 7-22 shows device initialization settings for 1-lane mode ADC data read using SDOUT.
Table 7-17 ADS9324C Initialization Sequence for 1-Lane Mode
STEP NUMBER REGISTER DESCRIPTION
SDI[23:16] = REG_ADDR SDI[15:0] = REG_ADDR DATA
1 Wait 30ms Power supply and voltage reference settling
2 0x01 0x0002 Software reset (optional)
3 Wait 1ms (optional) Optional delay
4 0x02 0x0001 Select ADS93x4C Common regbank
5 0x0A 0x0032 User programs this register based on system requirements. 0x0032 selects ADC conversion data size of 16b, and 1-lane mode data output on SDOUT pin.