SLVSLU1 June   2026 ADS9324C

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Input Clamp Protection Circuit
      3. 7.3.3  Analog Input Impedance
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  ADC Transfer Function
      6. 7.3.6  Reference
      7. 7.3.7  Open Wire Safe Mode
      8. 7.3.8  System Offset Calibration
      9. 7.3.9  System Gain Calibration
      10. 7.3.10 ADC Gain and Offset Error Calibration
      11. 7.3.11 Digital Filter
        1. 7.3.11.1 System Phase Calibration
        2. 7.3.11.2 Block Average Filter
        3. 7.3.11.3 Moving Average Filter
        4. 7.3.11.4 Low-Pass FIR Filter
      12. 7.3.12 Digital Window Comparator
      13. 7.3.13 Alarm Modes
      14. 7.3.14 Data Interface
        1. 7.3.14.1 ADC Channel Modes
        2. 7.3.14.2 Daisy Chain
        3. 7.3.14.3 Diagnostic Flags
        4. 7.3.14.4 ADC Output Data Randomizer
        5. 7.3.14.5 Test Patterns for Data Interface
        6. 7.3.14.6 Digital Output Drive Strength Control
        7. 7.3.14.7 Digital Output Delay Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Mode
      4. 7.4.4 Programming
        1. 7.4.4.1 Register Write Operation
        2. 7.4.4.2 Register Read Operation
        3. 7.4.4.3 Initialization Example - DOUT Lane Configuration
        4. 7.4.4.4 Initialization Example - Digital Filter
        5. 7.4.4.5 Initialization Example - Common Mode Error Correction
        6. 7.4.4.6 Initialization Example - ADC Calibration
        7. 7.4.4.7 Initialization Example - Test Pattern Mode
  9. 8 Register Maps
    1. 8.1 ADS93xx Common Registers
    2. 8.2 AIN1 - AIN8 Channel Registers
    3. 8.3 AIN9 - AIN16 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 16S Battery Cell Voltage Monitoring
    2. 9.2 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
        1. 9.3.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 12.1 Tape and Reel Information

7.3.4 Programmable Gain Amplifier (PGA)

The ADS93x4C features a programmable gain amplifier (PGA) at the every analog input channel. The PGA supports both single-ended and differential inputs with a bipolar signal swing. In differential-input mode, the ADS93x4C can take maximum common mode voltage of ±40V. In signal-ended mode, the maximum common mode voltage supported is ± RANGE 2 . Table 7-1 lists the supported analog input ranges. Configure the analog input range independently for each channel with the INPUT_RANGE_AINn[2:0] register fields in PGA_CONFIG_AINx registers.

Each analog input channel features an antialiasing, low-pass filter (LPF) at the output of the PGA. Table 7-2 lists the various programmable LPF options available in the ADS9324C, corresponding to the analog input range. The following illustrates the frequency responses for low-bandwidth and wide-bandwidth LPF configurations. Select the analog input bandwidth for the each analog input channels with the PGA_SEL bit field in the PGA_BW_SEL_AINn registers. By default, the all PGA are in low-bandwidth mode.

Table 7-1 Analog Input Ranges
INPUT TYPE RANGE INPUT_RANGE_AINx CM_RANGE_AINx
Single-ended ±50V 6 5
Single-ended ±25V 1 5
Single-ended ±12.5V 5 5
Single-ended ±10V 4 5
Single-ended ±6.25V 3 5
Single-ended ±5V 0 5
Single-ended ±2.5V 2 5
Differential ±25V 1 0
Differential ±12.5V 5 0
Differential ±10V 4 0
Differential ±6.25V 3 0
Differential ±5V 0 0
Differential ±2.5V 2 0
Single-ended open wire safe ±12.5V 5 6
Single-ended open wire safe ±10V 4 6
Single-ended open wire safe ±6.25V 3 6
Single-ended open wire safe ±5V 0 6
Single-ended open wire safe ±2.5V 2 6
Table 7-2 Low-Pass Filter Corner Frequency
LPF PGA_BW_SEL_AINn ANALOG INPUT RANGE CORNER FREQUENCY (–3dB)
Low-bandwidth 0 All input ranges 25.5kHz
Wide-bandwidth 1 ±2.5V 280kHz
±5V 325kHz
±6.25V 300kHz
±10V, ±12.5V 350kHz
±25V, ±50V 400kHz