SLVSLY3 June   2026 SN74UVP1G07

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 3 ns.

The outputs are measured individually with one input transition per measurement.

TEST RL CL ΔV VCC
tpd 20KΩ 5pF 0.07 V 0.7V
0.08 V 0.8 V
10pF 0.1 V 1.0V
5KΩ 10pF 0.12 V 1.2 V
15pF 0.15 V 1.5V
0.18 V 1.8 V
30pF 0.2 V 2.5V
0.3 V 3.3 V
SN74UVP1G07 Load Circuit for Open-Drain Outputs
(1) CL includes probe and test-fixture capacitance.
(2) RL = 5kΩ or 20kΩ for enable and disable time measurement. RL = 1MΩ for measuring propagation delays, setup and hold times, and pulse width.
Figure 6-1 Load Circuit for Open-Drain Outputs
SN74UVP1G07 Voltage Waveforms Propagation Delays
(1) If RL = 5kΩ, the time between tPLZ and tPZL is the same as disable and enable time.
(2) If RL = 1MΩ, tPLZ and tPZL are the same as tpd.
Figure 6-2 Voltage Waveforms Propagation Delays