SLVUBI1 May   2021

 

  1.   Trademarks
  2. 1TPS7H4002EVM-CVAL Overview
    1. 1.1 Features
    2. 1.2 Applications
  3. 2TPS7H4002EVM-CVAL Default Configuration
  4. 3TPS7H4002EVM-CVAL Initial Setup
  5. 4TPS7H4002EVM-CVAL Testing
    1. 4.1 Output Voltage Regulation
    2. 4.2 Output Voltage Ripple
    3. 4.3 Soft Start-up
    4. 4.4 Transient Response to Positive/Negative Load Step (0 A to 3A to 0A)
    5. 4.5 Input Voltage Ripple
    6. 4.6 Loop Frequency Response
    7. 4.7 Current Limiting
  6. 5TPS7H4002EVM-CVAL EVM Schematic
  7. 6TPS7H4002EVM-CVAL Bill of Materials (BOM)
  8. 7Board Layout

7 Board Layout

Figure 7-1 through Figure 7-11 illustrate the layer stack of the TPS7H4002EVM-CVAL board.

GUID-20210517-CA0I-S5CR-P4Z9-8MCR3GSWXZS7-low.pngFigure 7-1 Top Overlay
GUID-20210517-CA0I-2DJ8-ZVLT-3PNZVVQSRVHP-low.pngFigure 7-2 Top Solder
GUID-20210517-CA0I-2JRP-WVFR-5HNHLCKLNXLS-low.pngFigure 7-3 Layer 1 -Top Layer
GUID-20210517-CA0I-K45N-S9LS-XF1HBC3RCWWP-low.pngFigure 7-4 Layer 2- GND
GUID-20210517-CA0I-4PZN-WQRG-BMGLTVCCSTWB-low.pngFigure 7-5 Layer Three - Signal
GUID-20210517-CA0I-NBBS-ZM6C-M9R0JSS6MZVZ-low.pngFigure 7-6 Layer Four -Bottom Layer
GUID-20210517-CA0I-NB0S-VLD6-XZXKTVLR091G-low.pngFigure 7-7 Bottom Solder
GUID-20210517-CA0I-7SB9-D8SP-8QDJ78MRQDCP-low.pngFigure 7-8 Bottom Overlay
GUID-20210517-CA0I-RHF3-FWPM-TTGXQL0L1FDZ-low.pngFigure 7-9 Drill Drawing
GUID-20210517-CA0I-KHHR-RSB4-0NPB0H85D90N-low.pngFigure 7-10 Drill Table
GUID-20210517-CA0I-LNHP-T1XG-JH8T4NFL8DBT-low.pngFigure 7-11 Board Dimensions