SLVUBX8B October   2020  – December 2021 TPS2661

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 EVM Applications
  3. 2Description
  4. 3Schematic
  5. 4General Configurations
    1. 4.1 Physical Access
    2. 4.2 Test Equipment and Setup
      1. 4.2.1 Power Supplies
      2. 4.2.2 Meters
      3. 4.2.3 Oscilloscope
      4. 4.2.4 Loads
  6. 5Test Setup and Procedures
    1. 5.1 Overload Protection Test
    2. 5.2 Output Short-Circuit Test
    3. 5.3 Input Undervoltage Protection Test
    4. 5.4 Output Undervoltage Protection Test
    5. 5.5 Output Overvoltage Protection Test
    6. 5.6 TPS26612 Overload Protection Test
    7. 5.7 Current Limiting for VIN < –Vs
    8. 5.8 Surge Protection Test (Current Input, CH1)
    9. 5.9 Surge Protection Test (Analog Output, CH2)
  7. 6EVAL Board Assembly Drawings and Layout Guidelines
    1. 6.1 PCB Drawings
  8. 7Bill Of Materials (BoM)
  9. 8Revision History

5.9 Surge Protection Test (Analog Output, CH2)

Use the following instructions to perform surge test on the analog output in channel-2:

  1. Set dual polarity regulated power supply to +15 V : 0 V : –15 V and apply the power at connector J8
  2. Connect load resistor of 2 kΩ at the output
  3. Adjust the potentiometer R12 to set 10 V at the input of TPS26612
  4. Use UCS500N to generate surge pulses. Set the test voltage to ±1 kV and coupling impedance to 42 Ω as specified by IEC61000-4-5 to check the signal line transient immunity
  5. Connect the surge pulse generator UCS500N at J9 and enable it
  6. Observe the waveforms using an oscilloscope
Figure 5-15 and Figure 5-16 show surge performance for current inputs with TPS26610 on the TPS2661EVM eFuse evaluation board.
GUID-20210223-CA0I-5QS0-DRXB-FNDL3BKX449F-low.png Figure 5-15 IEC61000-4-5 (+1 kV, 42 Ω) Signal Line Surge Immunity With TVS3301 at Output of CH2
GUID-20210223-CA0I-XHPR-NLTK-TW1H0D5G6DGW-low.png Figure 5-16 IEC61000-4-5 (–1 kV, 42 Ω) Signal Line Surge Immunity With TVS3301 at Output of CH2