Product details


FET Internal Ron (Typ) (mOhm) 7500 Vin (Min) (V) -50 Vin (Max) (V) 50 Vabsmax_cont (V) 55 Current limit (Min) (A) 0.025 Current limit (Max) (A) 0.035 Overcurrent response Current limiting Fault response Auto Retry UL recognition open-in-new Find other eFuses & hot swap controllers

Package | Pins | Size

SOT-23-THN (DDF) 8 8 mm² 2.9 x 2.8 open-in-new Find other eFuses & hot swap controllers


  • ±50-V operating voltage, ±55-V absolute maximum
  • Integrated fixed bipolar 32-mA current limit
  • Allows 2x current limit at startup
  • 50% space savings compared to a typical discrete protection circuit
  • Low R-on: 7.5-Ω typical
  • Low Iq (< 100 nA) - current drawn from loop when powered from external supply
  • Protection against miswiring conditions on IN and OUT
  • Protection during signal line surge IEC61000-4-5 (with external TVS)
  • Criteria-A EFT (IEC61000-4-4) immunity (with external TVS)
  • Supports loop testing without supply (TPS26610 only)
  • HART compliant
  • Enable control
  • SGOOD for system health monitoring
  • Thermal shutdown
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The TPS2661x is a compact, feature rich, fully integrated current loop protector suitable for analog inputs, analog outputs, sensor transmitters, HART Inputs and UART IO protection. It provides Universal Input protection for ±20 mA, 0 to 20 mA, 4-20 mA. Low RON of 7.5 Ω minimizes drop in the current loop, thereby extending operating range and supporting operation even with lower voltage power supplies. The device can withstand and protect the loads from positive and negative supply voltages up to ±50 V. The MODE pin allows flexibility to enable 2x current limit through the device to enable proper startup of two wire transmitters. Device is capable of operating from an external bipolar supply as low as ± 2.25 V to ±20 V. It can also be powered from unipolar supplies as low as 3 V to 30 V. TPS26610 device features loop power mode to facilitate loop testing in un-powered state without ±Vs supplies.

The device also protects the system from output side miswiring in Analog Outputs and sensor transmitters by turning off the current path. The internal robust protection control blocks along with the 50-V rating of the TPS2661x helps to protect against surge (IEC61000-4-5) and EFT (IEC61000-4-4) transients for signal lines. The device greatly reduces system footprint by its 2.9 mm × 1.6 mm 8-pin SOT-23 package.

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Technical documentation

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Type Title Date
* Data sheet TPS2661x: 50 V, Universal 4 - 20 mA, ±20-mA Current Loop Protector with Input/Output Miswiring Protection datasheet (Rev. B) May 06, 2021
Application note New Approach to Protect 4–20 mA, ±20-mA Analog Input Jul. 06, 2021
User guide TPS2661EVM: Evaluation Module for TPS2661x Current-Loop Protector (Rev. A) Mar. 05, 2021
Certificate TPS2661EVM EU RoHS Declaration of Conformity (DoC) (Rev. A) Feb. 17, 2021
Application note Enabling Smarter, Integrated Protection for 4-20mA Current Loops with eFuses Dec. 11, 2020
Functional safety information TPS266x Functional Safety FIT Rate and Failure Mode Distribution Dec. 16, 2019

Design & development

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Hardware development

document-generic User guide
The TPS2661EVM allows reference circuit evaluation of TPS26611 and TPS26612 current-loop protectors. The TPS2661 product is a 50-V, universal (±20-mA, 0-mA to 20-mA, 4-mA to 20-mA) current-loop protector with integrated fixed bipolar 30-mA current limit and output overvoltage protection (...)
  • Supports bidirectional current loops with 0-V to ± 50-V operating range (with external VCC)
  • Fixed ILIMIT = ±30 mA ±15%
  • Enable (EN) pin control
  • Part status reporting through SGOODb pin
  • Protection against input-side miswiring

Design tools & simulation

SLVMDF3.ZIP (122 KB) - PSpice Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
SOT-23-THIN (DDF) 8 View options

Ordering & quality

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