SLVUC72C October   2021  – November 2022 TPSI3050-Q1

 

  1.   Abstract
  2.   Trademarks
  3.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  4. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  5. 2Connection Descriptions
  6. 3Operating Modes
    1. 3.1 Two-Wire Mode
    2. 3.2 Three-Wire Mode
  7. 4Load Configurations
  8. 5Schematic
  9. 6Layout
  10. 7Bill of Materials
  11. 8Revision History

3.1 Two-Wire Mode

Figure 3-1 Two-Wire Mode Simplified Schematic

In two-wire mode, the TPSI3050-Q1 can be controlled using two pins, EN and VSSP. When EN is greater or equal to 6.5 V, power is drive to the device. When the EN voltage is high, power gets delivered into the secondary side of the device. When EN is low, then power transfer into the secondary side stops and the MOSFETs or SCRs turns off.

To configure the EVM for two-wire mode, the following changes must be made:

  1. Remove J2-Header. Leave VDDP floating with Cin to VSSP.
  2. Supply the EN voltage using the terminal block J1.

Figure 3-2 provides a visual representation of how to configure the board for the two-wire mode:

Figure 3-2 Two-Wire Mode Setup
Table 3-1 Power Selection for Two-Wire Mode
J4-HeaderIEN
PXFR #1 (7.32 kΩ)1.9 mA
PXFR #2 (20 kΩ)6. 8 mA

Measurements

Figure 3-3 shows the powering up delay from EN rising to VDDM and VDDP rising using the highest power transfer PXFR #2 (20 kΩ) in two-wire mode. The power up delay is directly related to the power transfer selection and to the capacitors from VDDH to VDDM and VDDM to VSSS. The delay from EN to VDDM is 1.222 ms and the delay from EN to VDDH is 1.322 ms. Figure 3-3 shows the delay from EN rising to VDRV rising using the highest power transfer PXFR #2 (20 kΩ) in two-wire mode. The delay from EN to VDRV is 2.689 ms. Figure 3-5 shows the delay from EN falling to VDRV falling. The delay is 2.441 us.

Figure 3-3 Two-Wire Mode Powering Up
Figure 3-5 Two-Wire Mode Switching OFF
Figure 3-4 Two-Wire Mode Switching ON